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| author | cvs2svn <> | 2003-04-02 16:55:27 +0000 |
|---|---|---|
| committer | cvs2svn <> | 2003-04-02 16:55:27 +0000 |
| commit | 010b654fac6c49ac2c734ee4151c641fbe49b403 (patch) | |
| tree | c0e95dc0d9dd32c47f11e69b460587f21a69bf00 /include/gdb | |
| parent | 8ed0d1ced5ea081b1d3091e2c04b595c555f98b5 (diff) | |
| download | cygnal-010b654fac6c49ac2c734ee4151c641fbe49b403.tar.gz cygnal-010b654fac6c49ac2c734ee4151c641fbe49b403.tar.bz2 cygnal-010b654fac6c49ac2c734ee4151c641fbe49b403.zip | |
This commit was manufactured by cvs2svn to create branchcagney_frameaddr-20030403-branchpoint
'cagney_frameaddr-20030403-branch'.
Sprout from cagney_framebase-20030326-branch 2003-03-25 20:56:02 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2003-04-02 16:55:26 UTC Bob Wilson <bob.wilson@acm.org> ' * xtensa-config.h: Remove comment indicating that this is a':
include/ChangeLog
include/dis-asm.h
include/elf/ChangeLog
include/elf/arm.h
include/elf/common.h
include/elf/xtensa.h
include/gdb/ChangeLog
include/gdb/sim-arm.h
include/xtensa-config.h
include/xtensa-isa-internal.h
include/xtensa-isa.h
Diffstat (limited to 'include/gdb')
| -rw-r--r-- | include/gdb/ChangeLog | 4 | ||||
| -rw-r--r-- | include/gdb/sim-arm.h | 34 |
2 files changed, 37 insertions, 1 deletions
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog index 97c2f443c..9a216a0f3 100644 --- a/include/gdb/ChangeLog +++ b/include/gdb/ChangeLog @@ -1,3 +1,7 @@ +2003-03-27 Nick Clifton <nickc@redhat.com> + + * sim-arm.h (sim_arm_regs): Add iWMMXt registers. + 2003-03-20 Nick Clifton <nickc@redhat.com> * sim-arm.h (sim_arm_regs): Add Maverick co-processor diff --git a/include/gdb/sim-arm.h b/include/gdb/sim-arm.h index fae11f0b1..5598f73fa 100644 --- a/include/gdb/sim-arm.h +++ b/include/gdb/sim-arm.h @@ -72,7 +72,39 @@ enum sim_arm_regs SIM_ARM_MAVERIC_COP0R13_REGNUM, SIM_ARM_MAVERIC_COP0R14_REGNUM, SIM_ARM_MAVERIC_COP0R15_REGNUM, - SIM_ARM_MAVERIC_DSPSC_REGNUM + SIM_ARM_MAVERIC_DSPSC_REGNUM, + SIM_ARM_IWMMXT_COP0R0_REGNUM, + SIM_ARM_IWMMXT_COP0R1_REGNUM, + SIM_ARM_IWMMXT_COP0R2_REGNUM, + SIM_ARM_IWMMXT_COP0R3_REGNUM, + SIM_ARM_IWMMXT_COP0R4_REGNUM, + SIM_ARM_IWMMXT_COP0R5_REGNUM, + SIM_ARM_IWMMXT_COP0R6_REGNUM, + SIM_ARM_IWMMXT_COP0R7_REGNUM, + SIM_ARM_IWMMXT_COP0R8_REGNUM, + SIM_ARM_IWMMXT_COP0R9_REGNUM, + SIM_ARM_IWMMXT_COP0R10_REGNUM, + SIM_ARM_IWMMXT_COP0R11_REGNUM, + SIM_ARM_IWMMXT_COP0R12_REGNUM, + SIM_ARM_IWMMXT_COP0R13_REGNUM, + SIM_ARM_IWMMXT_COP0R14_REGNUM, + SIM_ARM_IWMMXT_COP0R15_REGNUM, + SIM_ARM_IWMMXT_COP1R0_REGNUM, + SIM_ARM_IWMMXT_COP1R1_REGNUM, + SIM_ARM_IWMMXT_COP1R2_REGNUM, + SIM_ARM_IWMMXT_COP1R3_REGNUM, + SIM_ARM_IWMMXT_COP1R4_REGNUM, + SIM_ARM_IWMMXT_COP1R5_REGNUM, + SIM_ARM_IWMMXT_COP1R6_REGNUM, + SIM_ARM_IWMMXT_COP1R7_REGNUM, + SIM_ARM_IWMMXT_COP1R8_REGNUM, + SIM_ARM_IWMMXT_COP1R9_REGNUM, + SIM_ARM_IWMMXT_COP1R10_REGNUM, + SIM_ARM_IWMMXT_COP1R11_REGNUM, + SIM_ARM_IWMMXT_COP1R12_REGNUM, + SIM_ARM_IWMMXT_COP1R13_REGNUM, + SIM_ARM_IWMMXT_COP1R14_REGNUM, + SIM_ARM_IWMMXT_COP1R15_REGNUM }; #ifdef __cplusplus |