This commit was manufactured by cvs2svn to create branchcagney_x86i386-20030821-branchpoint

'cagney_x86i386-20030821-branch'.

Sprout from gdb_6_0-branch 2003-06-22 16:35:52 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'gdb_6_0-branch'.'
Cherrypick from master 2003-08-21 14:03:23 UTC Nick Clifton <nickc@redhat.com> 'Add PGI extensions':
    ChangeLog
    MAINTAINERS
    Makefile.def
    Makefile.in
    Makefile.tpl
    config-ml.in
    config.if
    config.sub
    config/ChangeLog
    config/gettext.m4
    config/progtest.m4
    configure
    configure.in
    include/ChangeLog
    include/bfdlink.h
    include/coff/ChangeLog
    include/coff/ecoff.h
    include/coff/i860.h
    include/coff/pe.h
    include/coff/ti.h
    include/coff/xcoff.h
    include/demangle.h
    include/dis-asm.h
    include/elf/ChangeLog
    include/elf/dwarf2.h
    include/elf/mips.h
    include/elf/mmix.h
    include/elf/mn10300.h
    include/elf/msp430.h
    include/elf/ppc.h
    include/elf/reloc-macros.h
    include/elf/s390.h
    include/elf/v850.h
    include/nlm/ChangeLog
    include/nlm/internal.h
    include/opcode/ChangeLog
    include/opcode/alpha.h
    include/opcode/arc.h
    include/opcode/cgen.h
    include/opcode/d10v.h
    include/opcode/d30v.h
    include/opcode/h8300.h
    include/opcode/i370.h
    include/opcode/i386.h
    include/opcode/i860.h
    include/opcode/mips.h
    include/opcode/mn10300.h
    include/opcode/or32.h
    include/opcode/pj.h
    include/opcode/ppc.h
    include/opcode/s390.h
    include/opcode/sparc.h
    include/opcode/tic80.h
    include/opcode/v850.h
    include/xtensa-config.h
    mkinstalldirs
    src-release
    symlink-tree

1 files changed, 24 insertions, 0 deletions

diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 71c204c81..cb3a99a4e 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -1302,6 +1302,30 @@ static const template i386_optab[] = {
 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 
+/* Prescott New Instructions.  */
+
+{"addsubpd",  2, 0x660fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"addsubps",  2, 0xf20fd0,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"fisttp",    1, 0xdf,      1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} },
+/* Intel Syntax */
+{"fisttpd",   1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"fisttpq",   1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"fisttpll",  1, 0xdd,      1, CpuPNI, FP|Modrm,	{ LLongMem, 0, 0} },
+{"haddpd",    2, 0x660f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"haddps",    2, 0xf20f7c,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubpd",    2, 0x660f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"hsubps",    2, 0xf20f7d,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"lddqu",     2, 0xf20ff0,  X, CpuPNI, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
+{"monitor",   0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+/* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */
+{"monitor",   3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, Reg32} },
+{"movddup",   2, 0xf20f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movshdup",  2, 0xf30f16,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"movsldup",  2, 0xf30f12,  X, CpuPNI, FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
+{"mwait",     0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ 0, 0, 0} },
+/* Need to ensure only "mwait %eax,%ecx" is accepted.  */
+{"mwait",     2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt,	{ Reg32, Reg32, 0} },
+
 /* AMD 3DNow! instructions.  */
 
 {"prefetch", 1, 0x0f0d,	   0, Cpu3dnow, FP|Modrm,		{ ByteMem, 0, 0 } },