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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-23 20:12:52 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-23 20:12:52 +0000 |
| commit | 1acdf7f3c7f2e23860af1f58b004cbd6e71292f4 (patch) | |
| tree | f1047ef4ae5085f0f86137b6bb48648e5fd62e03 /include/opcode/mips.h | |
| parent | b5627d2ebc4a63c7c0cf040ceb7523c1cd6d4990 (diff) | |
| download | cygnal-1acdf7f3c7f2e23860af1f58b004cbd6e71292f4.tar.gz cygnal-1acdf7f3c7f2e23860af1f58b004cbd6e71292f4.tar.bz2 cygnal-1acdf7f3c7f2e23860af1f58b004cbd6e71292f4.zip | |
include/opcode/
* mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
gas/
* config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments.
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 9d241e847..e62ecd6e6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1811,7 +1811,7 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RD) + "G" 5-bit destination register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) "+D" combined destination register ("G") and sel ("H") for CP0 ops, for pretty-printing in disassembly only |