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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:54 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-07-07 09:32:54 +0000 |
| commit | 579ba5dd46357d603659934c38937e3c74dca555 (patch) | |
| tree | 3dc02e566f1ef42cae5baf5b25a56f80e07c535b /include/opcode/mips.h | |
| parent | ddbe02c4185407c934c504b6c141bf924f4b4052 (diff) | |
| download | cygnal-579ba5dd46357d603659934c38937e3c74dca555.tar.gz cygnal-579ba5dd46357d603659934c38937e3c74dca555.tar.bz2 cygnal-579ba5dd46357d603659934c38937e3c74dca555.zip | |
include/opcode/
* mips.h: Remove documentation of "+D" and "+T".
opcodes/
* mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
and "+T" handling. Check for a "0" suffix when deciding whether to
use coprocessor 0 names. In that case, also check for ",H" selectors.
gas/
* config/tc-mips.c (validate_mips_insn, validate_micromips_insn)
(mips_ip): Remove "+D" and "+T" handling.
gas/testsuite/
* gas/mips/lb.d, gas/mips/sb.d: Use coprocessor register names
for LWC0 and SWC0.
Diffstat (limited to 'include/opcode/mips.h')
| -rw-r--r-- | include/opcode/mips.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 68cd9b6d7..7ad60cb05 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -448,8 +448,6 @@ struct mips_opcode "e" 5 bit vector register byte specifier (OP_*_VECBYTE) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. Macro instructions: "A" General 32 bit expression @@ -489,7 +487,6 @@ struct mips_opcode "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only MCU ASE usage: "~" 12 bit offset (OP_*_OFFSET12) @@ -543,7 +540,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: "1234" - "ABCDEFGHIJPQSTXZ" + "ABCEFGHIJPQSXZ" "abcjpstxz" */ @@ -1816,8 +1813,6 @@ extern const int bfd_mips16_num_opcodes; "E" 5-bit target register (MICROMIPSOP_*_RT) "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - "+D" combined source register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only Macro instructions: "A" general 32 bit expression @@ -1859,7 +1854,7 @@ extern const int bfd_mips16_num_opcodes; following), for quick reference when adding more: "j" "" - "ABCDEFGHI" + "ABCEFGHI" "" Extension character sequences used so far ("m" followed by the |