This commit was manufactured by cvs2svn to create branchcagney_bigcore-20040122-branchpoint

'cagney_bigcore-20040122-branch'.

Sprout from ezannoni_pie-20030916-branch 2003-09-16 01:47:54 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch'
Cherrypick from master 2004-01-19 18:28:58 UTC Mark Kettenis <kettenis@gnu.org> '* common.h (NT_OPENBSD_IDENT): Define.':
    COPYING.NEWLIB
    ChangeLog
    Makefile.def
    Makefile.in
    Makefile.tpl
    config-ml.in
    config/ChangeLog
    config/acinclude.m4
    config/acx.m4
    config/gettext.m4
    configure
    configure.in
    gettext.m4
    include/ChangeLog
    include/ChangeLog-9103
    include/aout/ChangeLog
    include/aout/stab.def
    include/bfdlink.h
    include/coff/ChangeLog
    include/coff/ChangeLog-9103
    include/coff/internal.h
    include/demangle.h
    include/dis-asm.h
    include/elf/ChangeLog
    include/elf/ChangeLog-9103
    include/elf/common.h
    include/elf/frv.h
    include/elf/m32r.h
    include/elf/mips.h
    include/elf/mmix.h
    include/elf/ppc.h
    include/elf/sh.h
    include/elf/xtensa.h
    include/fibheap.h
    include/floatformat.h
    include/gdb/ChangeLog
    include/gdb/callback.h
    include/gdb/sim-frv.h
    include/hp-symtab.h
    include/obstack.h
    include/opcode/ChangeLog
    include/opcode/ChangeLog-9103
    include/opcode/h8300.h
    include/opcode/m68k.h
    include/opcode/mips.h
    include/opcode/mmix.h
    ltconfig
    src-release

1 files changed, 26 insertions, 4 deletions

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 65434a778..5c3ddfcd7 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -236,11 +236,24 @@ struct mips_opcode
    "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
 	Enforces: 0 <= pos < 32.
    "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
-	Requires that "+A" occur first to set position.
+	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 0 < (pos+size) <= 32.
    "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
-	Requires that "+A" occur first to set position.
+	Requires that "+A" or "+E" occur first to set position.
 	Enforces: 0 < (pos+size) <= 32.
+	(Also used by "dext" w/ different limits, but limits for
+	that are checked by the M_DEXT macro.)
+   "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
+	Enforces: 32 <= pos < 64.
+   "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
+   "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
+	Requires that "+A" or "+E" occur first to set position.
+	Enforces: 32 < (pos+size) <= 64.
 
    Floating point instructions:
    "D" 5 bit destination register (OP_*_FD)
@@ -265,7 +278,8 @@ struct mips_opcode
 
    Macro instructions:
    "A" General 32 bit expression
-   "I" 32 bit immediate
+   "I" 32 bit immediate (value placed in imm_expr).
+   "+I" 32 bit immediate (value placed in imm2_expr).
    "F" 64 bit floating point constant in .rdata
    "L" 64 bit floating point constant in .lit8
    "f" 32 bit floating point constant
@@ -292,7 +306,7 @@ struct mips_opcode
 
    Extension character sequences used so far ("+" followed by the
    following), for quick reference when adding more:
-   "ABCD"
+   "ABCDEFGHI"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -385,6 +399,7 @@ struct mips_opcode
 #define INSN_ISA32                0x00000020
 #define INSN_ISA64                0x00000040
 #define INSN_ISA32R2              0x00000080
+#define INSN_ISA64R2              0x00000100
 
 /* Masks used for MIPS-defined ASEs.  */
 #define INSN_ASE_MASK		  0x0000f000
@@ -432,6 +447,8 @@ struct mips_opcode
 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 
 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
+#define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
+
 
 /* CPU defines, use instead of hardcoding processor number. Keep this
    in sync with bfd/archures.c in order for machine selection to work.  */
@@ -460,6 +477,7 @@ struct mips_opcode
 #define CPU_MIPS32R2	33
 #define CPU_MIPS5       5
 #define CPU_MIPS64      64
+#define CPU_MIPS64R2	65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
@@ -542,11 +560,14 @@ enum
   M_DDIV_3I,
   M_DDIVU_3,
   M_DDIVU_3I,
+  M_DEXT,
+  M_DINS,
   M_DIV_3,
   M_DIV_3I,
   M_DIVU_3,
   M_DIVU_3I,
   M_DLA_AB,
+  M_DLCA_AB,
   M_DLI,
   M_DMUL,
   M_DMUL_I,
@@ -572,6 +593,7 @@ enum
   M_LB_AB,
   M_LBU_A,
   M_LBU_AB,
+  M_LCA_AB,
   M_LD_A,
   M_LD_OB,
   M_LD_AB,