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| author | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:56:34 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2013-03-20 16:56:34 +0000 |
| commit | 0fe1b31bca6f1cbb9b3b9fbade71ea37c7eaf6eb (patch) | |
| tree | ad61081160f753f73b0cdcfa283f0e12f74d224a /include/opcode/tic6x-opcode-table.h | |
| parent | de2e02904ef3f4bdb5e7f959bd82f8c76f8aa10a (diff) | |
| download | cygnal-0fe1b31bca6f1cbb9b3b9fbade71ea37c7eaf6eb.tar.gz cygnal-0fe1b31bca6f1cbb9b3b9fbade71ea37c7eaf6eb.tar.bz2 cygnal-0fe1b31bca6f1cbb9b3b9fbade71ea37c7eaf6eb.zip | |
PR gas/15082
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
Diffstat (limited to 'include/opcode/tic6x-opcode-table.h')
| -rw-r--r-- | include/opcode/tic6x-opcode-table.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h index abebd3c17..e9cfab917 100644 --- a/include/opcode/tic6x-opcode-table.h +++ b/include/opcode/tic6x-opcode-table.h @@ -75,7 +75,7 @@ #define ORREGD12 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORXREGD12 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 1, 2, 2 } #define ORREGD1234 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 2, 3, 4 } -#define ORREGD1324 { tic6x_operand_regpair, 8, tic6x_rw_read, 1, 3, 2, 4 } +#define ORXREGD1324 { tic6x_operand_xregpair, 8, tic6x_rw_read, 1, 3, 2, 4 } #define OWREGD910 { tic6x_operand_regpair, 8, tic6x_rw_write, 9, 9, 10, 10 } #define ORCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_read, 1, 1, 0, 0 } #define OWCREG1 { tic6x_operand_ctrl, 4, tic6x_rw_write, 1, 1, 0, 0 } @@ -1154,11 +1154,11 @@ INSNE(mpy, m_s5_xsl16_si, m, mpy, 1616_m, C62X, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, scst, 0), ENC(src2, reg, 1), ENC(dst, reg, 2))) -INSN(mpydp, m, mpy, mpydp, C67X, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x0e), FIX(x, 0)), - OP3(ORREGD1234, ORREGD1324, OWREGD910), - ENC4(ENC(s, fu, 0), ENC(src1, reg, 0), ENC(src2, reg, 1), - ENC(dst, reg, 2))) +INSN(mpydp, m, mpy, mpydp, C67X, 0, + FIX1(FIX(op, 0x0e)), + OP3(ORREGD1234, ORXREGD1324, OWREGD910), + ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0), + ENC(src2, reg, 1), ENC(dst, reg, 2))) INSN(mpyh, m, mpy, 1616_m, C62X, 0, FIX1(FIX(op, 0x01)), @@ -2520,7 +2520,7 @@ INSNE(zero, d_sub, d, 1_or_2_src, 1cycle, C62X, #undef OWDREGD5 #undef ORREGD12 #undef ORXREGD12 -#undef ORREGD1234 +#undef ORXREGD1234 #undef ORREGD1324 #undef OWREGD910 #undef ORCREG1 |