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| author | Jeff Johnston <jjohnstn@redhat.com> | 2015-05-26 15:19:13 -0400 |
|---|---|---|
| committer | Corinna Vinschen <corinna@vinschen.de> | 2015-05-27 13:30:19 +0200 |
| commit | 132030fcf203a50c5c85f162135bb92b08021bf5 (patch) | |
| tree | 6e51331d0adcfba964600b82bedaaab782ae07ef /libgloss/ChangeLog | |
| parent | 324bd1170642cf2c2fd963350aa428e0cc5a88fb (diff) | |
| download | cygnal-132030fcf203a50c5c85f162135bb92b08021bf5.tar.gz cygnal-132030fcf203a50c5c85f162135bb92b08021bf5.tar.bz2 cygnal-132030fcf203a50c5c85f162135bb92b08021bf5.zip | |
Fix interrupt handling for or1k.
- During interrupt handling the PICSR, table pointers and current
interrupt line have been saved in incorrect registers and/or stored on
the stack.
- Save the pointer in r16/r18, PICSR in r20 and the current interrupt
line in r22. Those are callee-saved registers, so that the register
values will be preserved.
* or1k/interruts-asm.S: Change registers to callee-saved.
Diffstat (limited to 'libgloss/ChangeLog')
| -rw-r--r-- | libgloss/ChangeLog | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/libgloss/ChangeLog b/libgloss/ChangeLog index 9988189be..1ca803fcb 100644 --- a/libgloss/ChangeLog +++ b/libgloss/ChangeLog @@ -1,3 +1,7 @@ +2015-05-26 Stefan Wallentowitz <stefan.wallentowitz@tum.de> + + * or1k/interruts-asm.S: Change registers to callee-saved. + 2015-05-18 Nick Clifton <nickc@redhat.com> * msp430/msp430-sim.ld (.stack): Add an assertion to make sure |