diff options
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/ChangeLog | 247 | ||||
| -rw-r--r-- | include/opcode/alpha.h | 4 | ||||
| -rw-r--r-- | include/opcode/cgen.h | 6 | ||||
| -rw-r--r-- | include/opcode/d10v.h | 4 | ||||
| -rw-r--r-- | include/opcode/d30v.h | 1 | ||||
| -rw-r--r-- | include/opcode/hppa.h | 971 | ||||
| -rw-r--r-- | include/opcode/i386.h | 537 | ||||
| -rw-r--r-- | include/opcode/m68k.h | 33 | ||||
| -rw-r--r-- | include/opcode/mips.h | 23 | ||||
| -rw-r--r-- | include/opcode/mn10300.h | 23 | ||||
| -rw-r--r-- | include/opcode/pj.h | 46 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 3 |
12 files changed, 1375 insertions, 523 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 79bc3cc7c..e8acc1c84 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,250 @@ +1999-12-30 Andrew Haley <aph@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg. + +2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Qualify intel mode far call and jmp with x_Suf. + +1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add JumpAbsolute qualifier to all non-intel mode + indirect jumps and calls. Add FF/3 call for intel mode. + +Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add new operand types. Add new instruction formats. + +Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" + instruction. + +1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_ISA5): New. + +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): New. + +1999-10-29 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_AR): Define. + +1999-10-18 Michael Meissner <meissner@cygnus.com> + + * alpha.h (alpha_num_opcodes): Convert to unsigned. + (alpha_num_operands): Ditto. + +Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> + + * hppa.h (pa_opcodes): Add load and store cache control to + instructions. Add ordered access load and store. + + * hppa.h (pa_opcode): Add new entries for addb and addib. + + * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. + + * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. + +Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. + +Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" + and "be" using completer prefixes. + + * hppa.h (pa_opcodes): Add initializers to silence compiler. + + * hppa.h: Update comments about character usage. + +Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning + up the new fstw & bve instructions. + +Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store + instructions. + + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + + * hppa.h (pa_opcodes): Add long offset double word load/store + instructions. + + * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and + stores. + + * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. + + * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. + + * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. + + * hppa.h (pa_opcodes): Add new syntax "be" instructions. + + * hppa.h (pa_opcodes): Note use of 'M' and 'L'. + + * hppa.h (pa_opcodes): Add support for "b,l". + + * hppa.h (pa_opcodes): Add support for "b,gate". + +Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Use 'fX' for first register operand + in xmpyu. + + * hppa.h (pa_opcodes): Fix mask for probe and probei. + + * hppa.h (pa_opcodes): Fix mask for depwi. + +Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as + an explicit output argument. + +Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. + Add a few PA2.0 loads and store variants. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + +1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Move %st to top of table, and split off + other fp reg entries. + (i386_float_regtab): To here. + +Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args + by 'f'. + + * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. + Add supporting args. + + * hppa.h: Document new completers and args. + * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, + uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 + extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions + pmenb and pmdis. + + * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, + hshr, hsub, mixh, mixw, permh. + + * hppa.h (pa_opcodes): Change completers in instructions to + use 'c' prefix. + + * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, + hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. + + * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, + fnegabs to use 'I' instead of 'F'. + +1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. + Document pf2iw and pi2fw as athlon insns. Remove pswapw. + Alphabetically sort PIII insns. + +Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + +Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, + and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. + + * hppa.h: Document 64 bit condition completers. + +Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Change condition args to use '?' prefix. + +1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add DefaultSize modifier to all insns + that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, + sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. + +Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". + + * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. + + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. + +1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford <dledford@redhat.com> + +Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + 1999-04-14 Doug Evans <devans@casey.cygnus.com> * cgen.h (CGEN_ATTR): Delete member num_nonbools. diff --git a/include/opcode/alpha.h b/include/opcode/alpha.h index d18eb0445..6f31e9ae0 100644 --- a/include/opcode/alpha.h +++ b/include/opcode/alpha.h @@ -54,7 +54,7 @@ struct alpha_opcode in the order in which the disassembler should consider instructions. */ extern const struct alpha_opcode alpha_opcodes[]; -extern const int alpha_num_opcodes; +extern const unsigned alpha_num_opcodes; /* Values defined for the flags field of a struct alpha_opcode. */ @@ -135,7 +135,7 @@ struct alpha_operand the operands field of the alpha_opcodes table. */ extern const struct alpha_operand alpha_operands[]; -extern const int alpha_num_operands; +extern const unsigned alpha_num_operands; /* Values defined for the flags field of a struct alpha_operand. */ diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 84542a37c..2a5fd0da8 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1037,6 +1037,12 @@ extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); /* Return value of base part of INSN. */ #define CGEN_INSN_BASE_VALUE(insn) \ CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) /* Macro instructions. Macro insns aren't real insns, they map to one or more real insns. diff --git a/include/opcode/d10v.h b/include/opcode/d10v.h index 4b74c9862..7c6d32ddf 100644 --- a/include/opcode/d10v.h +++ b/include/opcode/d10v.h @@ -176,6 +176,10 @@ extern const struct d10v_operand d10v_operands[]; /* general purpose register */ #define OPERAND_GPR (0x40000) +/* special imm3 values with range restricted to -2 <= imm3 <= 3 */ +/* needed for rac/rachi */ +#define RESTRICTED_NUM3 (0x80000) + /* Structure to hold information about predefined registers. */ struct pd_reg { diff --git a/include/opcode/d30v.h b/include/opcode/d30v.h index b828dab32..64c7c3634 100644 --- a/include/opcode/d30v.h +++ b/include/opcode/d30v.h @@ -118,6 +118,7 @@ struct d30v_opcode #define LONG_2b 59 /* LONG_2 with modifier of 3 */ #define LONG_D 60 /* for DBRAI*/ #define LONG_Db 61 /* for repeati*/ +#define SHORT_AR 62 /* like SHORT_AA but only accept register as third parameter */ /* the execution unit(s) used */ int unit; diff --git a/include/opcode/hppa.h b/include/opcode/hppa.h index 30ccb6ccf..1c41ff07c 100644 --- a/include/opcode/hppa.h +++ b/include/opcode/hppa.h @@ -43,8 +43,12 @@ struct pa_opcode unsigned long int mask; /* ... in these bits. */ char *args; enum pa_arch arch; + char flags; }; +/* Enable/disable strict syntax checking. Not currently used, but will + be necessary for PA2.0 support in the future. */ +#define FLAG_STRICT 0x1 /* All hppa opcodes are 32 bits. @@ -53,8 +57,9 @@ struct pa_opcode particular opcode in order for an instruction to be an instance of that opcode. - The args component is a string containing one character - for each operand of the instruction. + The args component is a string containing one character for each operand of + the instruction. Characters used as a prefix allow any second character to + be used without conflicting with the main operand characters. Bit positions in this description follow HP usage of lsb = 31, "at" is lsb of field. @@ -65,9 +70,9 @@ struct pa_opcode In the args field, the following characters are unused: - ' "#$% *+- ./ :; ' - ' [\] ' - ' { } ' + ' " & - / 34 6789:;< > @' + ' C M [\] ' + ' e g l y } ' Here are all the characters: @@ -79,20 +84,10 @@ Kinds of operands: x integer register field at 15. b integer register field at 10. t integer register field at 31. - y floating point register field at 31 + a integer register field at 10 and 15 (for PERMH) 5 5 bit immediate at 15. s 2 bit space specifier at 17. S 3 bit space specifier at 18. - c indexed load completer. - C short load and store completer. - Y Store Bytes Short completer - < non-negated compare/subtract conditions. - a compare/subtract conditions - d non-negated add conditions - & logical instruction conditions - U unit instruction conditions - > shift/extract/deposit conditions. - ~ bvb,bb conditions V 5 bit immediate value at 31 i 11 bit immediate value at 31 j 14 bit immediate value at 31 @@ -101,20 +96,28 @@ Kinds of operands: N nullification for spop and copr instructions w 12 bit branch displacement W 17 bit branch displacement (PC relative) + X 22 bit branch displacement (PC relative) z 17 bit branch displacement (just a number, not an address) Also these: + . 2 bit shift amount at 25 + * 4 bit shift amount at 25 p 5 bit shift count at 26 (to support the SHD instruction) encoded as 31-p + ~ 6 bit shift count at 20,22:26 encoded as 63-~. P 5 bit bit position at 26 + q 6 bit bit position at 20,22:26 T 5 bit field length at 31 (encoded as 32-T) + % 6 bit field length at 23,27:31 (variable extract/deposit) + | 6 bit field length at 19,27:31 (fixed extract/deposit) A 13 bit immediate at 18 (to support the BREAK instruction) ^ like b, but describes a control register - Z System Control Completer (to support LPA, LHA, etc.) + ! sar (cr11) register D 26 bit immediate at 31 (to support the DIAG instruction) + $ 9 bit immediate at 28 (to support POPBTS) - f 3 bit Special Function Unit identifier at 25 + v 3 bit Special Function Unit identifier at 25 O 20 bit Special Function Unit operation split between 15 bits at 20 and 5 bits at 31 o 15 bit Special Function Unit operation at 20 @@ -129,37 +132,126 @@ Also these: I Source Floating Point Operand Format Completer encoded 1 bits at 20 (for 0xe format FP instructions) G Destination Floating Point Operand Format Completer encoded 2 bits at 18 - M Floating-Point Compare Conditions (encoded as 5 bits at 31) - ? non-negated/negated compare/subtract conditions. - @ non-negated/negated add conditions. - ! non-negated add conditions. + H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' + (very similar to 'F') - s 2 bit space specifier at 17. - b register field at 10. r 5 bit immediate value at 31 (for the break instruction) (very similar to V above, except the value is unsigned instead of low_sign_ext) R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions) (same as r above, except the value is in a different location) + U 10 bit immediate value at 15 (for SSM, RSM on pa2.0) Q 5 bit immediate value at 10 (a bit position specified in the bb instruction. It's the same as r above, except the value is in a different location) - | shift/extract/deposit conditions when used in a conditional branch - -And these (PJH) for PA-89 F.P. registers and instructions: - - v a 't' operand type extended to handle L/R register halves. - E a 'b' operand type extended to handle L/R register halves. - X an 'x' operand type extended to handle L/R register halves. - J a 'b' operand type further extended to handle extra 1.1 registers - K a 'x' operand type further extended to handle extra 1.1 registers - 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub' - 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub' - 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub' - 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub') - 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub') - H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub' - (very similar to 'F') + B 5 bit immediate value at 10 (a bit position specified in + the bb instruction. Similar to Q, but 64bit handling is + different. + Z %r1 -- implicit target of addil instruction. + L ,%r2 completer for new syntax branch + { Source format completer for fcnv + _ Destination format completer for fcnv + h cbit for fcmp + = gfx tests for ftest + d 14bit offset for single precision FP long load/store. + # 14bit offset for double precision FP load long/store. + J Yet another 14bit offset with an unusual encoding. + K Yet another 14bit offset with an unusual encoding. + Y %sr0,%r31 -- implicit target of be,l instruction. + @ implicit immediate value of 0 + +Completer operands all have 'c' as the prefix: + + cx indexed load completer. + cm short load and store completer. + cq long load and store completer (like cm, but inserted into a + different location in the target instruction). + cs store bytes short completer. + ce long load/store completer for LDW/STW with a different encoding than the + others + cc load cache control hint + cd load and clear cache control hint + cC store cache control hint + co ordered access + + cp branch link and push completer + cP branch pop completer + cl branch link completer + cg branch gate completer + + cw read/write completer for PROBE + cW wide completer for MFCTL + cL local processor completer for cache control + cZ System Control Completer (to support LPA, LHA, etc.) + + ci correction completer for DCOR + ca add completer + cy 32 bit add carry completer + cY 64 bit add carry completer + cv signed overflow trap completer + ct trap on condition completer for ADDI, SUB + cT trap on condition completer for UADDCM + cb 32 bit borrow completer for SUB + cB 64 bit borrow completer for SUB + + ch left/right half completer + cH signed/unsigned saturation completer + cS signed/unsigned completer at 21 + c* permutation completer + +Condition operands all have '?' as the prefix: + + ?f Floating point compare conditions (encoded as 5 bits at 31) + + ?a add conditions + ?A 64 bit add conditions + ?@ add branch conditions followed by nullify + ?d non-negated add branch conditions + ?D negated add branch conditions + ?w wide mode non-negated add branch conditions + ?W wide mode negated add branch conditions + + ?s compare/subtract conditions + ?S 64 bit compare/subtract conditions + ?t non-negated compare and branch conditions + ?n 32 bit compare and branch conditions followed by nullify + ?N 64 bit compare and branch conditions followed by nullify + ?Q 64 bit compare and branch conditions for CMPIB instruction + + ?l logical conditions + ?L 64 bit logical conditions + + ?b branch on bit conditions + ?B 64 bit branch on bit conditions + + ?x shift/extract/deposit conditions + ?X 64 bit shift/extract/deposit conditions + ?y shift/extract/deposit conditions followed by nullify for conditional + branches + + ?u unit conditions + ?U 64 bit unit conditions + +Floating point registers all have 'f' as a prefix: + + ft target register at 31 + fT target register with L/R halves at 31 + fa operand 1 register at 10 + fA operand 1 register with L/R halves at 10 + fX Same as fA, except prints a space before register during disasm + fb operand 2 register at 15 + fB operand 2 register with L/R halves at 15 + fC operand 3 register with L/R halves at 16:18,21:23 + fe Like fT, but encoding is different. + +Float registers for fmpyadd and fmpysub: + + fi mult operand 1 register at 10 + fj mult operand 2 register at 15 + fk mult target register at 20 + fl add/sub operand register at 25 + fm add/sub target register at 31 + */ @@ -178,299 +270,562 @@ static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e static const struct pa_opcode pa_opcodes[] = { - /* pseudo-instructions */ -{ "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */ -{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */ -{ "comib", 0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/ -{ "comb", 0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */ -{ "addb", 0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */ -{ "addib", 0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/ -{ "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */ -{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */ -{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */ +{ "ldi", 0x34000000, 0xffe0c000, "j,x", pa10, 0},/* ldo val(r0),r */ + +{ "call", 0xe800f000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "call", 0xe800a000, 0xffe0e000, "nW", pa10, FLAG_STRICT}, +{ "ret", 0xe840d000, 0xfffffffd, "n", pa20, FLAG_STRICT}, + +{ "cmpib", 0xec000000, 0xfc000000, "?Qn5,b,w", pa20, FLAG_STRICT}, +{ "cmpib", 0x84000000, 0xf4000000, "?nn5,b,w", pa10, FLAG_STRICT}, +{ "comib", 0x84000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comib", 0x8c000000, 0xfc000000, "?nn5,b,w", pa10, 0}, /* comib{tf}*/ +{ "cmpb", 0x9c000000, 0xdc000000, "?Nnx,b,w", pa20, FLAG_STRICT}, +{ "cmpb", 0x80000000, 0xf4000000, "?nnx,b,w", pa10, FLAG_STRICT}, +{ "comb", 0x80000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "comb", 0x88000000, 0xfc000000, "?nnx,b,w", pa10, 0}, /* comb{tf} */ +{ "addb", 0xa0000000, 0xf4000000, "?Wnx,b,w", pa20, FLAG_STRICT}, +{ "addb", 0xa0000000, 0xfc000000, "?@nx,b,w", pa10, 0}, /* addb{tf} */ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addb", 0xa8000000, 0xfc000000, "?@nx,b,w", pa10, 0}, +{ "addib", 0xa4000000, 0xf4000000, "?Wn5,b,w", pa20, FLAG_STRICT}, +{ "addib", 0xa4000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +/* This entry is for the disassembler only. It will never be used by + assembler. */ +{ "addib", 0xac000000, 0xfc000000, "?@n5,b,w", pa10, 0}, /* addib{tf}*/ +{ "nop", 0x08000240, 0xffffffff, "", pa10, 0}, /* or 0,0,0 */ +{ "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10, 0}, /* or r,0,t */ +{ "mtsar", 0x01601840, 0xffe0ffff, "x", pa10, 0}, /* mtctl r,cr11 */ /* Loads and Stores for integer registers. */ -{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10}, -{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10}, -{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10}, -{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10}, -{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10}, -{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10}, -{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10}, -{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t", pa10}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10}, -{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t", pa10}, -{ "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t", pa10}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10}, -{ "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10}, -{ "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10}, -{ "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10}, -{ "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10}, + +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010e0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0000c0, 0xfc0013c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(s,b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x0c0010c0, 0xfc0013c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "ldd", 0x50000000, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c000080, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c0010a0, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x0c001080, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(s,b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x4c000000, 0xfc000000, "ceJ(b),x", pa10, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(s,b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x5c000004, 0xfc000006, "ceK(b),x", pa20, FLAG_STRICT}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c000040, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001060, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x0c001040, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c000000, 0xfc0013c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(s,b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001020, 0xfc1f33e0, "cocc@(b),t", pa20, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(s,b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x0c001000, 0xfc0013c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x0c0012c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, +{ "std", 0x70000000, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c0012a0, 0xfc0013ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x0c001280, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(s,b)", pa10, FLAG_STRICT}, +{ "stw", 0x6c000000, 0xfc000000, "cex,J(b)", pa10, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(s,b)", pa20, FLAG_STRICT}, +{ "stw", 0x7c000004, 0xfc000006, "cex,K(b)", pa20, FLAG_STRICT}, +{ "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001260, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "sth", 0x0c001240, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001220, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stb", 0x0c001200, 0xfc0013c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10, 0}, +{ "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10, 0}, +{ "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldwx", 0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldhx", 0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldbx", 0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldwa", 0x0c000180, 0xfc00d3c0, "cxccx(b),t", pa10, FLAG_STRICT}, +{ "ldwa", 0x0c001180, 0xfc00d3c0, "cmcc5(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0001c0, 0xfc0013c0, "cxcdx(b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(s,b),t", pa10, FLAG_STRICT}, +{ "ldcw", 0x0c0011c0, 0xfc0013c0, "cmcd5(b),t", pa10, FLAG_STRICT}, +{ "stwa", 0x0c0013a0, 0xfc00d3ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stwa", 0x0c001380, 0xfc00d3c0, "cmcCx,V(b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(s,b)", pa10, FLAG_STRICT}, +{ "stby", 0x0c001300, 0xfc0013c0, "cscCx,V(b)", pa10, FLAG_STRICT}, +{ "ldda", 0x0c000100, 0xfc00d3c0, "cxccx(b),t", pa20, FLAG_STRICT}, +{ "ldda", 0x0c001100, 0xfc00d3c0, "cmcc5(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c000140, 0xfc0013c0, "cxcdx(b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(s,b),t", pa20, FLAG_STRICT}, +{ "ldcd", 0x0c001140, 0xfc0013c0, "cmcd5(b),t", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013e0, 0xfc0033ff, "cocCx,@(b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stda", 0x0c0013c0, 0xfc0013c0, "cmcCx,V(b)", pa20, FLAG_STRICT}, +{ "ldwax", 0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, 0}, +{ "ldcwx", 0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldws", 0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldhs", 0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldbs", 0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "ldwas", 0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, 0}, +{ "ldcws", 0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "stws", 0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "sths", 0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, 0}, +{ "stbs", 0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, 0}, +{ "stwas", 0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, 0}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(s,b)", pa20, FLAG_STRICT}, +{ "stdby", 0x0c001340, 0xfc0013c0, "cscCx,V(b)", pa20, FLAG_STRICT}, +{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, 0}, +{ "stbys", 0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, 0}, /* Immediate instructions. */ -{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10}, -{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10}, -{ "addil", 0x28000000, 0xfc000000, "k,b", pa10}, +{ "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10, 0}, +{ "ldil", 0x20000000, 0xfc000000, "k,b", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b,Z", pa10, 0}, +{ "addil", 0x28000000, 0xfc000000, "k,b", pa10, 0}, /* Branching instructions. */ -{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10}, -{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10}, -{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10}, -{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10}, -{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10}, -{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10}, -{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10}, -{ "movb", 0xc8000000, 0xfc000000, "|nx,b,w", pa10}, -{ "movib", 0xcc000000, 0xfc000000, "|n5,b,w", pa10}, -{ "combt", 0x80000000, 0xfc000000, "<nx,b,w", pa10}, -{ "combf", 0x88000000, 0xfc000000, "<nx,b,w", pa10}, -{ "comibt", 0x84000000, 0xfc000000, "<n5,b,w", pa10}, -{ "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", pa10}, -{ "addbt", 0xa0000000, 0xfc000000, "!nx,b,w", pa10}, -{ "addbf", 0xa8000000, 0xfc000000, "!nx,b,w", pa10}, -{ "addibt", 0xa4000000, 0xfc000000, "!n5,b,w", pa10}, -{ "addibf", 0xac000000, 0xfc000000, "!n5,b,w", pa10}, -{ "bb", 0xc4004000, 0xfc004000, "~nx,Q,w", pa10}, -{ "bvb", 0xc0004000, 0xffe04000, "~nx,w", pa10}, +{ "b", 0xe8008000, 0xfc00e000, "cpnXL", pa20, FLAG_STRICT}, +{ "b", 0xe800a000, 0xfc00e000, "clnXL", pa20, FLAG_STRICT}, +{ "b", 0xe8000000, 0xfc00e000, "clnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8002000, 0xfc00e000, "cgnW,b", pa10, FLAG_STRICT}, +{ "b", 0xe8000000, 0xffe0e000, "nW", pa10, 0}, /* b,l foo,r0 */ +{ "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10, 0}, +{ "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10, 0}, +{ "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10, 0}, +{ "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10, 0}, +{ "bve", 0xe800f001, 0xfc1ffffd, "cpn(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800f000, 0xfc1ffffd, "cln(b)L", pa20, FLAG_STRICT}, +{ "bve", 0xe800d001, 0xfc1ffffd, "cPn(b)", pa20, FLAG_STRICT}, +{ "bve", 0xe800d000, 0xfc1ffffd, "n(b)", pa20, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(S,b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe4000000, 0xfc000000, "clnz(b),Y", pa10, FLAG_STRICT}, +{ "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "be", 0xe0000000, 0xfc000000, "nz(b)", pa10, 0}, +{ "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10, 0}, +{ "movb", 0xc8000000, 0xfc000000, "?ynx,b,w", pa10, 0}, +{ "movib", 0xcc000000, 0xfc000000, "?yn5,b,w", pa10, 0}, +{ "combt", 0x80000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "combf", 0x88000000, 0xfc000000, "?tnx,b,w", pa10, 0}, +{ "comibt", 0x84000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "comibf", 0x8c000000, 0xfc000000, "?tn5,b,w", pa10, 0}, +{ "addbt", 0xa0000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addbf", 0xa8000000, 0xfc000000, "?dnx,b,w", pa10, 0}, +{ "addibt", 0xa4000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "addibf", 0xac000000, 0xfc000000, "?dn5,b,w", pa10, 0}, +{ "bb", 0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?Bnx,B,w", pa20, FLAG_STRICT}, +{ "bb", 0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT}, +{ "bb", 0xc4004000, 0xfc004000, "?bnx,Q,w", pa10, 0}, +{ "bvb", 0xc0004000, 0xffe04000, "?bnx,w", pa10, 0}, +{ "clrbts", 0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "popbts", 0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT}, +{ "pushnom", 0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT}, +{ "pushbts", 0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT}, /* Computation Instructions */ -{ "add", 0x08000600, 0xfc000fe0, "dx,b,t", pa10}, -{ "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", pa10}, -{ "addc", 0x08000700, 0xfc000fe0, "dx,b,t", pa10}, -{ "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", pa10}, -{ "sub", 0x08000400, 0xfc000fe0, "ax,b,t", pa10}, -{ "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subb", 0x08000500, 0xfc000fe0, "ax,b,t", pa10}, -{ "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", pa10}, -{ "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", pa10}, -{ "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", pa10}, -{ "ds", 0x08000440, 0xfc000fe0, "ax,b,t", pa10}, -{ "comclr", 0x08000880, 0xfc000fe0, "ax,b,t", pa10}, -{ "or", 0x08000240, 0xfc000fe0, "&x,b,t", pa10}, -{ "xor", 0x08000280, 0xfc000fe0, "&x,b,t", pa10}, -{ "and", 0x08000200, 0xfc000fe0, "&x,b,t", pa10}, -{ "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", pa10}, -{ "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", pa10}, -{ "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", pa10}, -{ "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", pa10}, -{ "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", pa10}, -{ "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", pa10}, -{ "addi", 0xb4000000, 0xfc000800, "di,b,x", pa10}, -{ "addio", 0xb4000800, 0xfc000800, "di,b,x", pa10}, -{ "addit", 0xb0000000, 0xfc000800, "di,b,x", pa10}, -{ "addito", 0xb0000800, 0xfc000800, "di,b,x", pa10}, -{ "subi", 0x94000000, 0xfc000800, "ai,b,x", pa10}, -{ "subio", 0x94000800, 0xfc000800, "ai,b,x", pa10}, -{ "comiclr", 0x90000000, 0xfc000800, "ai,b,x", pa10}, +{ "cmpclr", 0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT}, +{ "cmpclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT}, +{ "comclr", 0x08000880, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "or", 0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "or", 0x08000240, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "xor", 0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "xor", 0x08000280, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "and", 0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "and", 0x08000200, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "andcm", 0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT}, +{ "andcm", 0x08000000, 0xfc000fe0, "?lx,b,t", pa10, 0}, +{ "uxor", 0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT}, +{ "uxor", 0x08000380, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcm", 0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT}, +{ "uaddcm", 0x08000980, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "uaddcmt", 0x080009c0, 0xfc000fe0, "?ux,b,t", pa10, 0}, +{ "dcor", 0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT}, +{ "dcor", 0x08000b80, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "idcor", 0x08000bc0, 0xfc1f0fe0, "?ub,t", pa10, 0}, +{ "addi", 0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT}, +{ "addi", 0xb4000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addio", 0xb4000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addit", 0xb0000000, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "addito", 0xb0000800, 0xfc000800, "?ai,b,x", pa10, 0}, +{ "add", 0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT}, +{ "add", 0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT}, +{ "add", 0x08000600, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addl", 0x08000a00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addo", 0x08000e00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addc", 0x08000700, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "addco", 0x08000f00, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sub", 0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT}, +{ "sub", 0x08000400, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subo", 0x08000c00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subb", 0x08000500, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subbo", 0x08000d00, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subt", 0x080004c0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subto", 0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "ds", 0x08000440, 0xfc000fe0, "?sx,b,t", pa10, 0}, +{ "subi", 0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT}, +{ "subi", 0x94000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "subio", 0x94000800, 0xfc000800, "?si,b,x", pa10, 0}, +{ "cmpiclr", 0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT}, +{ "cmpiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT}, +{ "comiclr", 0x90000000, 0xfc000800, "?si,b,x", pa10, 0}, +{ "shladd", 0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT}, +{ "shladd", 0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT}, +{ "sh1add", 0x08000640, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addl", 0x08000a40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh1addo", 0x08000e40, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2add", 0x08000680, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addl", 0x08000a80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh2addo", 0x08000e80, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3add", 0x080006c0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addl", 0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10, 0}, +{ "sh3addo", 0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10, 0}, + +/* Subword Operation Instructions */ + +{ "hadd", 0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "havg", 0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT}, +{ "hshl", 0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT}, +{ "hshladd", 0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hshr", 0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT}, +{ "hshradd", 0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT}, +{ "hsub", 0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT}, +{ "mixh", 0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "mixw", 0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT}, +{ "permh", 0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT}, + /* Extract and Deposit Instructions */ -{ "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", pa10}, -{ "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", pa10}, -{ "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", pa10}, -{ "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", pa10}, -{ "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", pa10}, -{ "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", pa10}, -{ "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", pa10}, -{ "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", pa10}, -{ "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", pa10}, -{ "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", pa10}, -{ "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", pa10}, -{ "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", pa10}, -{ "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", pa10}, -{ "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", pa10}, +{ "shrpd", 0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT}, +{ "shrpd", 0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT}, +{ "shrpw", 0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT}, +{ "shrpw", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT}, +{ "vshd", 0xd0000000, 0xfc001fe0, "?xx,b,t", pa10, 0}, +{ "shd", 0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, 0}, +{ "extrd", 0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT}, +{ "extrd", 0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT}, +{ "extrw", 0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT}, +{ "extrw", 0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT}, +{ "vextru", 0xd0001000, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "vextrs", 0xd0001400, 0xfc001fe0, "?xb,T,x", pa10, 0}, +{ "extru", 0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "extrs", 0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10, 0}, +{ "depd", 0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT}, +{ "depd", 0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT}, +{ "depdi", 0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT}, +{ "depdi", 0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT}, +{ "depw", 0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT}, +{ "depw", 0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT}, +{ "depwi", 0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT}, +{ "zvdep", 0xd4000000, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "vdep", 0xd4000400, 0xfc001fe0, "?xx,T,b", pa10, 0}, +{ "zdep", 0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "dep", 0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10, 0}, +{ "zvdepi", 0xd4001000, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "vdepi", 0xd4001400, 0xfc001fe0, "?x5,T,b", pa10, 0}, +{ "zdepi", 0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10, 0}, +{ "depi", 0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10, 0}, /* System Control Instructions */ -{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10}, -{ "rfi", 0x00000c00, 0xffffffff, "", pa10}, -{ "rfir", 0x00000ca0, 0xffffffff, "", pa11}, -{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10}, -{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10}, -{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10}, -{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10}, -{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10}, -{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10}, -{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10}, -{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10}, -{ "sync", 0x00000400, 0xffffffff, "", pa10}, -{ "syncdma", 0x00100400, 0xffffffff, "", pa10}, -{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10}, -{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10}, -{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10}, -{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10}, -{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10}, -{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10}, -{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10}, -{ "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t", pa10}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10}, -{ "lha", 0x04001300, 0xfc003fc0, "Zx(b),t", pa10}, -{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10}, -{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)", pa10}, -{ "pitlb", 0x04000200, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "pitlb", 0x04000200, 0xfc001fdf, "Zx(b)", pa10}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)", pa10}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "pitlbe", 0x04000240, 0xfc001fdf, "Zx(b)", pa10}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10}, -{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10}, -{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10}, -{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10}, -{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "pdc", 0x04001380, 0xfc003fdf, "Zx(b)", pa10}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "fdc", 0x04001280, 0xfc003fdf, "Zx(b)", pa10}, -{ "fic", 0x04000280, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "fic", 0x04000280, 0xfc001fdf, "Zx(b)", pa10}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10}, -{ "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)", pa10}, -{ "fice", 0x040002c0, 0xfc001fdf, "Zx(S,b)", pa10}, -{ "fice", 0x040002c0, 0xfc001fdf, "Zx(b)", pa10}, -{ "diag", 0x14000000, 0xfc000000, "D", pa10}, +{ "break", 0x00000000, 0xfc001fe0, "r,A", pa10, 0}, +{ "rfi", 0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT}, +{ "rfi", 0x00000c00, 0xffffffff, "", pa10, 0}, +{ "rfir", 0x00000ca0, 0xffffffff, "", pa11, 0}, +{ "ssm", 0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "rsm", 0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT}, +{ "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10, 0}, +{ "mtsm", 0x00001860, 0xffe0ffff, "x", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10, 0}, +{ "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10, 0}, +{ "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10, 0}, +{ "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10, 0}, +{ "mtsarcm", 0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT}, +{ "mfia", 0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT}, +{ "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10, 0}, +{ "mfctl", 0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT}, +{ "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10, 0}, +{ "sync", 0x00000400, 0xffffffff, "", pa10, 0}, +{ "syncdma", 0x00100400, 0xffffffff, "", pa10, 0}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT}, +{ "probe", 0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT}, +{ "probei", 0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT}, +{ "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10, 0}, +{ "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10, 0}, +{ "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lpa", 0x04001340, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10, 0}, +{ "lha", 0x04001300, 0xfc003fc0, "cZx(b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10, 0}, +{ "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10, 0}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlb", 0x04001200, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlb", 0x04000200, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdtlbe", 0x04001240, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "pitlbe", 0x04000240, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10, 0}, +{ "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10, 0}, +{ "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "pdc", 0x04001380, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdc", 0x04001280, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fic", 0x04000280, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10, 0}, +{ "fdce", 0x040012c0, 0xfc003fdf, "cZx(b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10, 0}, +{ "fice", 0x040002c0, 0xfc001fdf, "cZx(b)", pa10, 0}, +{ "diag", 0x14000000, 0xfc000000, "D", pa10, 0}, +{ "idtlbt", 0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, +{ "iitlbt", 0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT}, + +/* These may be specific to certain versions of the PA. Joel claimed + they were 72000 (7200?) specific. However, I'm almost certain the + mtcpu/mfcpu were undocumented, but available in the older 700 machines. */ +{ "mtcpu", 0x14001600, 0xfc00ffff, "x,^", pa10, 0}, +{ "mfcpu", 0x14001A00, 0xfc00ffff, "^,x", pa10, 0}, +{ "tocen", 0x14403600, 0xffffffff, "", pa10, 0}, +{ "tocdis", 0x14401620, 0xffffffff, "", pa10, 0}, +{ "shdwgr", 0x14402600, 0xffffffff, "", pa10, 0}, +{ "grshdw", 0x14400620, 0xffffffff, "", pa10, 0}, /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either the Timex FPU or the Mustang ERS (not sure which) manual. */ -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)", pa11}, -{ "gfw", 0x04001680, 0xfc003fdf, "Zx(b)", pa11}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11}, -{ "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)", pa11}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfw", 0x04001680, 0xfc003fdf, "cZx(b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11, 0}, +{ "gfr", 0x04001a80, 0xfc003fdf, "cZx(b)", pa11, 0}, /* Floating Point Coprocessor Instructions */ - -{ "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v", pa10}, -{ "fldwx", 0x24000000, 0xfc001f80, "cx(b),v", pa10}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10}, -{ "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y", pa10}, -{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(s,b)", pa10}, -{ "fstwx", 0x24000200, 0xfc001f80, "cv,x(b)", pa10}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, -{ "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)", pa10}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10}, -{ "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)", pa10}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v", pa10}, -{ "fldws", 0x24001000, 0xfc001f80, "C5(b),v", pa10}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10}, -{ "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y", pa10}, -{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10}, -{ "fstws", 0x24001200, 0xfc001f80, "Cv,5(b)", pa10}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, -{ "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10}, -{ "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10}, -{ "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10}, -{ "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10}, -{ "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10}, -{ "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10}, -{ "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10}, -{ "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10}, -{ "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10}, -{ "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10}, -{ "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10}, -{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10}, -{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10}, -{ "fmpyfadd", 0xb8000000, 0xfc000020, "FE,X,3,v", pa20}, -{ "fmpynfadd", 0xb8000020, 0xfc000020, "FE,X,3,v", pa20}, -{ "fneg", 0x3000c000, 0xfc1fe7e0, "FE,v", pa20}, -{ "fneg", 0x3800c000, 0xfc1fe720, "FJ,v", pa20}, -{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "FE,v", pa20}, -{ "fnegabs", 0x3800e000, 0xfc1fe720, "FJ,v", pa20}, -{ "fcmp", 0x30000400, 0xfc00e7e0, "FME,X", pa10}, -{ "fcmp", 0x38000400, 0xfc00e720, "IMJ,K", pa10}, -{ "xmpyu", 0x38004700, 0xfc00e720, "E,X,v", pa11}, -{ "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11}, -{ "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11}, -{ "ftest", 0x30002420, 0xffffffff, "", pa10}, -{ "fid", 0x30000000, 0xffffffff, "", pa11}, - + +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(s,b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24001020, 0xfc1f33a0, "cocc@(b),fT", pa20, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24000000, 0xfc001380, "cxccx(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(s,b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x24001000, 0xfc001380, "cmcc5(b),fT", pa10, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x5c000000, 0xfc000004, "d(b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(s,b),fe", pa20, FLAG_STRICT}, +{ "fldw", 0x58000000, 0xfc000004, "cJd(b),fe", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(s,b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c001020, 0xfc1f33e0, "cocc@(b),ft", pa20, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c000000, 0xfc0013c0, "cxccx(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(s,b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x2c001000, 0xfc0013c0, "cmcc5(b),ft", pa10, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(s,b),x", pa20, FLAG_STRICT}, +{ "fldd", 0x50000002, 0xfc000002, "cq#(b),x", pa20, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001220, 0xfc1f33a0, "cocCfT,@(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24000200, 0xfc001380, "cxcCfT,x(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(s,b)", pa10, FLAG_STRICT}, +{ "fstw", 0x24001200, 0xfc001380, "cmcCfT,5(b)", pa10, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x7c000000, 0xfc000004, "fe,d(b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "cJfe,d(s,b)", pa20, FLAG_STRICT}, +{ "fstw", 0x78000000, 0xfc000004, "cJfe,d(b)", pa20, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001220, 0xfc1f33e0, "cocCft,@(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c000200, 0xfc0013c0, "cxcCft,x(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa10, FLAG_STRICT}, +{ "fstd", 0x2c001200, 0xfc0013c0, "cmcCft,5(b)", pa10, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqx,#(s,b)", pa20, FLAG_STRICT}, +{ "fstd", 0x70000002, 0xfc000002, "cqx,#(b)", pa20, FLAG_STRICT}, +{ "fldwx", 0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10, 0}, +{ "fldwx", 0x24000000, 0xfc001f80, "cxx(b),fT", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10, 0}, +{ "flddx", 0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10, 0}, +{ "fstwx", 0x24000200, 0xfc001f80, "cxfT,x(b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0}, +{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, 0}, +{ "fldws", 0x24001000, 0xfc001f80, "cm5(b),fT", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10, 0}, +{ "fldds", 0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10, 0}, +{ "fstws", 0x24001200, 0xfc001f80, "cmfT,5(b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0}, +{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10, 0}, +{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fsub", 0x38002600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fmpy", 0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fmpy", 0x38004600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fdiv", 0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "fdiv", 0x38006600, 0xfc00e720, "IfA,fB,fT", pa10, 0}, +{ "fsqrt", 0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fsqrt", 0x38008000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fabs", 0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fabs", 0x38006000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "frem", 0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0}, +{ "frem", 0x38008600, 0xfc00e720, "FfA,fB,fT", pa10, 0}, +{ "frnd", 0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "frnd", 0x3800a000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcpy", 0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10, 0}, +{ "fcpy", 0x38004000, 0xfc1fe720, "FfA,fT", pa10, 0}, +{ "fcnvff", 0x30000200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvff", 0x38000200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvxf", 0x30008200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvxf", 0x38008200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfx", 0x30010200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfx", 0x38010200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGfa,fT", pa10, 0}, +{ "fcnvfxt", 0x38018200, 0xfc1f8720, "FGfA,fT", pa10, 0}, +{ "fmpyfadd", 0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fmpynfadd", 0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fneg", 0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT}, +{ "fnegabs", 0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x30000200, 0xfc1c0720, "{_fa,fT", pa20, FLAG_STRICT}, +{ "fcnv", 0x38000200, 0xfc1c0720, "FGfA,fT", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc0007e0, "F?ffa,fb,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x38000400, 0xfc000720, "I?ffA,fB,h", pa20, FLAG_STRICT}, +{ "fcmp", 0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10, 0}, +{ "fcmp", 0x38000400, 0xfc00e720, "I?ffA,fB", pa10, 0}, +{ "xmpyu", 0x38004700, 0xfc00e720, "fX,fB,fT", pa11, 0}, +{ "fmpyadd", 0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "fmpysub", 0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11, 0}, +{ "ftest", 0x30002420, 0xffffffe0, ",=", pa20, FLAG_STRICT}, +{ "ftest", 0x30000420, 0xffff1fff, "m", pa20, FLAG_STRICT}, +{ "ftest", 0x30002420, 0xffffffff, "", pa10, 0}, +{ "fid", 0x30000000, 0xffffffff, "", pa11, 0}, + +/* Performance Monitor Instructions */ + +{ "pmdis", 0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT}, +{ "pmenb", 0x30000680, 0xffffffff, "", pa20, FLAG_STRICT}, /* Assist Instructions */ -{ "spop0", 0x10000000, 0xfc000600, "f,ON", pa10}, -{ "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10}, -{ "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10}, -{ "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10}, -{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t", pa10}, -{ "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t", pa10}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10}, -{ "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t", pa10}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)", pa10}, -{ "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)", pa10}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10}, -{ "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)", pa10}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t", pa10}, -{ "cldws", 0x24001000, 0xfc001e00, "uC5(b),t", pa10}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10}, -{ "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t", pa10}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10}, -{ "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)", pa10}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10}, -{ "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)", pa10}, +{ "spop0", 0x10000000, 0xfc000600, "v,ON", pa10, 0}, +{ "spop1", 0x10000200, 0xfc000600, "v,oNt", pa10, 0}, +{ "spop2", 0x10000400, 0xfc000600, "v,1Nb", pa10, 0}, +{ "spop3", 0x10000600, 0xfc000600, "v,0Nx,b", pa10, 0}, +{ "copr", 0x30000000, 0xfc000000, "u,2N", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, +{ "cldwx", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, 0}, +{ "clddx", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, +{ "cstwx", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, 0}, +{ "cstdx", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, +{ "cldws", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, 0}, +{ "cldds", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, +{ "cstws", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, 0}, +{ "cstds", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, 0}, +{ "cldw", 0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, +{ "cldw", 0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT}, +{ "cldd", 0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstw", 0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT}, +{ "cstd", 0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT}, }; #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0])) diff --git a/include/opcode/i386.h b/include/opcode/i386.h index ef8fece15..7bddbed4e 100644 --- a/include/opcode/i386.h +++ b/include/opcode/i386.h @@ -42,7 +42,6 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const template i386_optab[] = { #define X None -#define ReverseModrm (ReverseRegRegmem|Modrm) #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) @@ -84,45 +83,45 @@ static const template i386_optab[] = { { "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, { "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, /* move to/from control debug registers */ -{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32, 0} }, -{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32, 0} }, -{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32, 0} }, +{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, /* move with sign extend */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, NoSuf|ReverseModrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movsx", 2, 0x0fbf, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, /* move with zero extend */ -{"movzb", 2, 0x0fb6, X, wl_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzwl", 2, 0x0fb7, X, NoSuf|ReverseModrm, { Reg16|ShortMem, Reg32, 0} }, +{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, /* Intel Syntax */ -{"movzx", 2, 0x0fb7, X, w_Suf|ReverseModrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movzx", 2, 0x0fb6, X, b_Suf|ReverseModrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, /* push instructions */ -{"push", 1, 0x50, X, wl_Suf|ShortForm, { WordReg,0,0 } }, -{"push", 1, 0xff, 6, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, wl_Suf, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, wl_Suf, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, +{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, +{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* push all */ -{"pusha", 0, 0x60, X, wl_Suf, { 0, 0, 0 } }, +{"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, /* pop instructions */ -{"pop", 1, 0x58, X, wl_Suf|ShortForm, { WordReg,0,0 } }, -{"pop", 1, 0x8f, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0 } }, +{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm, { SReg2,0,0 } }, -{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm, { SReg3,0,0 } }, +{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* pop all */ -{"popa", 0, 0x61, X, wl_Suf, { 0, 0, 0 } }, +{"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, /* xchg exchange instructions xchg commutes: we allow both operand orders */ @@ -159,8 +158,8 @@ static const template i386_optab[] = { {"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} }, {"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} }, {"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, wl_Suf, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, wl_Suf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} }, {"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} }, {"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, {"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, @@ -250,9 +249,9 @@ static const template i386_optab[] = { These multiplies can only be selected with single operand forms. */ {"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, wl_Suf|ReverseModrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, wl_Suf|ReverseModrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, +{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, /* imul with 2 operands mimics imul with 3 by putting the register in both i.rm.reg & i.rm.regmem fields. regKludge enables this transformation. */ @@ -312,28 +311,31 @@ static const template i386_optab[] = { {"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, /* control transfer instructions */ -{"call", 1, 0xe8, X, wl_Suf|JumpDword, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, +{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, #define JUMP_PC_RELATIVE 0xeb {"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, {"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"jmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} }, {"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ret", 0, 0xc3, X, wl_Suf, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, wl_Suf, { Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, wl_Suf, { 0, 0, 0} }, -{"lret", 1, 0xca, X, wl_Suf, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, wl_Suf, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, wl_Suf, { 0, 0, 0} }, +{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, /* conditional jumps */ {"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, @@ -448,8 +450,8 @@ static const template i386_optab[] = { {"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, /* bit manipulation */ -{"bsf", 2, 0x0fbc, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, {"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, {"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, @@ -478,23 +480,23 @@ static const template i386_optab[] = { {"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, /* protection control */ -{"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, +{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, {"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, {"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, /* floating point instructions */ @@ -767,7 +769,7 @@ static const template i386_optab[] = { /* 486 extensions */ -{"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } }, +{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, {"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, @@ -782,10 +784,10 @@ static const template i386_optab[] = { {"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, {"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, {"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, -{"sysenter", 0, 0x0f34, X, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, +{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, /* Pentium Pro extensions */ {"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, @@ -794,166 +796,267 @@ static const template i386_optab[] = { {"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */ {"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */ -{"cmovo", 2, 0x0f40, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, wl_Suf|ReverseModrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, NoSuf|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} }, +{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* MMX instructions. */ -{"emms", 0, 0x0f77, X, NoSuf, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, NoSuf|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, NoSuf|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movq", 2, 0x0f6f, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, NoSuf|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"packssdw", 2, 0x0f6b, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x0f63, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x0f67, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x0ffc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x0ffd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x0ffe, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x0fec, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x0fed, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x0fdc, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x0fdd, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x0fdb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x0fdf, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x0fe5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x0fd5, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x0feb, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0ff1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0f71, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x0ff2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x0f72, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x0ff3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x0f73, 6, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x0fe1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x0f71, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x0fe2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x0f72, 4, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x0fd1, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x0f71, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x0fd2, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x0f72, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x0fd3, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x0f73, 2, NoSuf|Modrm, { Imm8, RegMMX, 0 } }, -{"psubb", 2, 0x0ff8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x0ff9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x0ffa, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x0fe8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x0fe9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x0fd8, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x0fd9, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x0f68, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x0f69, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x0f6a, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x0f60, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x0f61, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x0f62, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x0fef, X, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, - - +{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + + +/* PIII Katmai New Instructions / SIMD instructions */ + +{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, +{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, +{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + /* AMD 3DNow! instructions */ -#define AMD_3DNOW_OPCODE 0x0f0f - -{"prefetch", 1, 0x0f0d, 0, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, NoSuf|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, NoSuf, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, NoSuf|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + +{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ {NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ }; #undef X -#undef ReverseModrm #undef NoSuf #undef b_Suf #undef w_Suf #undef l_Suf +#undef d_Suf +#undef x_Suf #undef bw_Suf #undef bl_Suf #undef wl_Suf #undef sl_Suf +#undef sld_Suf +#undef sldx_Suf #undef bwl_Suf +#undef bwld_Suf #undef FP #undef l_FP +#undef d_FP +#undef x_FP #undef sl_FP +#undef sld_FP +#undef sldx_FP #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ @@ -961,6 +1064,8 @@ static const template i386_optab[] = { /* 386 register table */ static const reg_entry i386_regtab[] = { + /* make %st first as we test for it */ + {"st", FloatReg|FloatAcc, 0}, /* 8 bit regs */ {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, @@ -1030,16 +1135,7 @@ static const reg_entry i386_regtab[] = { {"tr5", Test, 5}, {"tr6", Test, 6}, {"tr7", Test, 7}, - /* float registers */ - {"st(0)", FloatReg|FloatAcc, 0}, - {"st", FloatReg|FloatAcc, 0}, - {"st(1)", FloatReg, 1}, - {"st(2)", FloatReg, 2}, - {"st(3)", FloatReg, 3}, - {"st(4)", FloatReg, 4}, - {"st(5)", FloatReg, 5}, - {"st(6)", FloatReg, 6}, - {"st(7)", FloatReg, 7}, + /* mmx and simd registers */ {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, @@ -1047,7 +1143,26 @@ static const reg_entry i386_regtab[] = { {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, {"mm6", RegMMX, 6}, - {"mm7", RegMMX, 7} + {"mm7", RegMMX, 7}, + {"xmm0", RegXMM, 0}, + {"xmm1", RegXMM, 1}, + {"xmm2", RegXMM, 2}, + {"xmm3", RegXMM, 3}, + {"xmm4", RegXMM, 4}, + {"xmm5", RegXMM, 5}, + {"xmm6", RegXMM, 6}, + {"xmm7", RegXMM, 7} +}; + +static const reg_entry i386_float_regtab[] = { + {"st(0)", FloatReg|FloatAcc, 0}, + {"st(1)", FloatReg, 1}, + {"st(2)", FloatReg, 2}, + {"st(3)", FloatReg, 3}, + {"st(4)", FloatReg, 4}, + {"st(5)", FloatReg, 5}, + {"st(6)", FloatReg, 6}, + {"st(7)", FloatReg, 7} }; #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ diff --git a/include/opcode/m68k.h b/include/opcode/m68k.h index ecb3f95dd..3208b77f4 100644 --- a/include/opcode/m68k.h +++ b/include/opcode/m68k.h @@ -1,5 +1,5 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. - Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. + Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1999 Free Software Foundation. This file is part of GDB, GAS, and the GNU binutils. @@ -36,6 +36,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68851 0x080 #define cpu32 0x100 /* e.g., 68332 */ #define mcf5200 0x200 +#define mcf5206e 0x400 +#define mcf5307 0x800 /* handy aliases */ #define m68040up (m68040 | m68060) @@ -43,6 +45,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) +#define mcf (mcf5200 | mcf5206e | mcf5307) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) @@ -87,7 +90,7 @@ struct m68k_opcode_alias operand; the second, the place it is stored. */ /* Kinds of operands: - Characters used: AaBCcDdFfIJkLlMmnOopQqRrSsTtUVvWXYZ0123|*~%;@!&$?/<>#^+- + Characters used: AaBCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWXYZ0123|*~%;@!&$?/<>#^+- D data register only. Stored as 3 bits. A address register only. Stored as 3 bits. @@ -121,6 +124,9 @@ struct m68k_opcode_alias C the CCR. No need to store it; this is just for filtering validity. S the SR. No need to store, just as with CCR. U the USP. No need to store, just as with CCR. + E the ACC. No need to store, just as with CCR. + G the MACSR. No need to store, just as with CCR. + H the MASK. No need to store, just as with CCR. I Coprocessor ID. Not printed if 1. The Coprocessor ID is always extracted from the 'd' field of word one, which means that an extended @@ -170,6 +176,9 @@ struct m68k_opcode_alias for both caches. Used in cinv and cpush. Always stored in position "d". + u Any register, with ``upper'' or ``lower'' specification. Used + in the mac instructions with size word. + The remainder are all stored as 6 bits using an address mode and a register number; they differ in which addressing modes they match. @@ -260,6 +269,8 @@ struct m68k_opcode_alias */ /* Places to put an operand, for non-general operands: + Characters used: BbCcDdghijkLlMmNnostWw123456789 + s source, low bits of first word. d dest, shifted 9 in first word 1 second word, shifted 12 @@ -293,6 +304,24 @@ struct m68k_opcode_alias C floating point coprocessor constant - 7 bits. Also used for static K-factors... j Movec register #, stored in 12 low bits of second word. + m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word + and remaining 3 bits of register shifted 9 bits in first word. + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split + with MSB shifted 6 bits in first word and remaining 3 bits of + register shifted 9 bits in first word. No upper/lower + indication is done.) Use with `R' or `u' format. + o For M[S]ACw; 4 bits shifted 12 in second word (like `1'). + Indicate upper/lower in 1 bit shifted 7 bits in second word. + Use with `R' or `u' format. + M For M[S]ACw; 4 bits in low bits of first word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + N For M[S]ACw; 4 bits in low bits of second word. Indicate + upper/lower in 1 bit shifted 6 bits in second word. Use with + `R' or `u' format. + h shift indicator (scale factor), 1 bit shifted 10 in second word Places to put operand, for general operands: d destination, shifted 6 bits in first word diff --git a/include/opcode/mips.h b/include/opcode/mips.h index f0a8c7ef9..3f9207ff3 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -308,6 +308,7 @@ struct mips_opcode #define INSN_ISA3 0x00000003 /* MIPS ISA 4 instruction (R8000). */ #define INSN_ISA4 0x00000004 +#define INSN_ISA5 0x00000005 /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -319,6 +320,28 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 +/* 32-bit code running on a ISA3+ CPU. */ +#define INSN_GP32 0x00001000 + +/* Test for membership in an ISA including chip specific ISAs. + INSN is pointer to an element of the opcode table; ISA is the + specified ISA to test against; and CPU is the CPU specific ISA + to test, or zero if no CPU specific ISA test is desired. */ + +#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ + ((((insn)->membership & INSN_ISA) != 0 \ + && ((insn)->membership & INSN_ISA) <= isa \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + || (cpu == 4650 \ + && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == 4010 \ + && ((insn)->membership & INSN_4010) != 0) \ + || ((cpu == 4100 \ + || cpu == 4111 \ + ) \ + && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == 3900 \ + && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. * diff --git a/include/opcode/mn10300.h b/include/opcode/mn10300.h index 34e4b0b43..12f03670f 100644 --- a/include/opcode/mn10300.h +++ b/include/opcode/mn10300.h @@ -117,6 +117,23 @@ extern const struct mn10300_operand mn10300_operands[]; #define MN10300_OPERAND_RELAX 0x4000 +#define MN10300_OPERAND_USP 0x8000 + +#define MN10300_OPERAND_SSP 0x10000 + +#define MN10300_OPERAND_MSP 0x20000 + +#define MN10300_OPERAND_PC 0x40000 + +#define MN10300_OPERAND_EPSW 0x80000 + +#define MN10300_OPERAND_RREG 0x100000 + +#define MN10300_OPERAND_XRREG 0x200000 + +#define MN10300_OPERAND_PLUS 0x400000 + +#define MN10300_OPERAND_24BIT 0x800000 /* Opcode Formats. */ #define FMT_S0 1 @@ -129,10 +146,16 @@ extern const struct mn10300_operand mn10300_operands[]; #define FMT_D2 8 #define FMT_D4 9 #define FMT_D5 10 +#define FMT_D6 11 +#define FMT_D7 12 +#define FMT_D8 13 +#define FMT_D9 14 +#define FMT_D10 15 /* Variants of the mn10300 which have additional opcodes. */ #define MN103 300 #define AM30 300 +#define AM33 330 #endif /* MN10300_H */ diff --git a/include/opcode/pj.h b/include/opcode/pj.h new file mode 100644 index 000000000..8759b627e --- /dev/null +++ b/include/opcode/pj.h @@ -0,0 +1,46 @@ +/* Definitions for decoding the picoJava opcode table. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Steve Chamberlain of Transmeta (sac@pobox.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +/* Names used to describe the type of instruction arguments, used by + the assembler and disassembler. Attributes are encoded in various fields. */ + +/* reloc size pcrel uns */ +#define O_N 0 +#define O_16 (1<<4 | 2 | (0<<6) | (0<<3)) +#define O_U16 (1<<4 | 2 | (0<<6) | (1<<3)) +#define O_R16 (2<<4 | 2 | (1<<6) | (0<<3)) +#define O_8 (3<<4 | 1 | (0<<6) | (0<<3)) +#define O_U8 (3<<4 | 1 | (0<<6) | (1<<3)) +#define O_R8 (4<<4 | 1 | (0<<6) | (0<<3)) +#define O_R32 (5<<4 | 4 | (1<<6) | (0<<3)) +#define O_32 (6<<4 | 4 | (0<<6) | (0<<3)) + +#define ASIZE(x) ((x) & 0x7) +#define PCREL(x) (!!((x) & (1<<6))) +#define UNS(x) (!!((x) & (1<<3))) + + +typedef struct +{ + short opcode; + short opcode_next; + char len; + unsigned char arg[2]; + const char *name; +} pj_opc_info_t; diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a9e3b24ab..974f0dfa5 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -85,6 +85,9 @@ extern const int powerpc_num_opcodes; for the assembler's -many option, and it eliminates duplicates). */ #define PPC_OPCODE_ANY (0200) +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE (0400) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) |