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* Add s390 supportNick Clifton2001-02-102-0/+134
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* Binutils portion of fix for syntax array elements when maxPatrick Macdonald2001-02-022-9/+11
| | | | | | | | | | | | | operands is greater than 127. 2001-02-02 Patrick Macdonald <patrickm@redhat.com> * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. * m32r-desc.h: Regenerate.
* Fix swapgs instruction.Alan Modra2001-01-242-3/+7
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* Adds assembly and dis-assembly support for the HPPA wideAlan Modra2001-01-142-21/+35
| | | | mode, 16 bit forms of ldi, ldo, ldw and stw instructions.
* * i386.c (md_assemble): Check cpu_flags even for nullary instructions.Jan Hubicka2001-01-132-3/+9
| | | | | | | * i386.h (i386_optab): Fix pusha and ret templates. * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret templates.
* Updated ARC assembler from arccores.comNick Clifton2001-01-112-106/+155
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* * i386.h (pinsrw): Add.Jan Hubicka2001-01-102-4/+12
| | | | | | | (pshufw): Remove. (cvttpd2dq): Fix operands. (cvttps2dq): Likewise. (movq2q): Rename to movdq2q.
* Fix "movnti"Alan Modra2001-01-102-6/+10
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* 2001-01-09 Jeff Johnston <jjohnstn@redhat.com>Jeff Johnston2001-01-092-3/+15
| | | | | | | * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number of operands (unsigned char or unsigned short). (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
* * tc-i386.c (md_assemble): Handle third byte of the opcode as prefix.Jan Hubicka2001-01-052-5/+9
| | | | * i386.h (i386_optab): Make [sml]fence template to use immext field.
* * tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,Jan Hubicka2001-01-032-4/+173
| | | | | | | | | CpuUnknown): Renumber (CpuP4, CpuSSE2): New. (CpuUnknownFlags): Add CpuP4 and CpuSSE2 * i386.h (i386_optab): Fix 64bit pushf template; Add instructions introduced by Pentium4
* * configure.in: Add support for x86_64 and x86_64-*-linux-gnu*Jan Hubicka2000-12-302-272/+452
| | | | | | | | | | | | | * NEWS: Add x86_64. * i386.h (i386_optab): Add "rex*" instructions; add swapgs; disable jmp/call far direct instructions for 64bit mode; add syscall and sysret; disable registers for 0xc6 template. Add 'q' suffixes to extendable instructions, disable obsoletted instructions, add new sign/zero extension ones. (i386_regtab): Add extended registers. (*Suf): Add No_qSuf. (q_Suf, wlq_Suf, bwlq_Suf): New.
* * tc-i386.h (i386_target_format): Define even for ELFs.Jan Hubicka2000-12-202-107/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
* Fix Formatting.Nick Clifton2000-12-122-4/+7
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* * tc-i386.c (md_assemble): Refuse 's' and 'l' suffixes in the intelJan Hubicka2000-12-111-76/+60
| | | | | | | | | | | | | | mode; convert 'd' suffix to 's' or 'l'; remove all DWORD_MNEM_SUFFIX references. (intel_e09_1): Convert QWORD to 'l' suffix for FP operations; refuse otherwise. * tc-i386.h (DWORD_MNEM_SUFFIX): Kill. (No_dSuf): Kill. * i386.h (*_Suf): Remove No_dSuf. (d_suf, wld_Suf,sld_Suf, sldx_Suf, bwld_Suf, d_FP, sld_FP, sldx_FP) Remove. (i386_optab): Remove 'd' in the suffixes.
* Add MIPS SB1 machineNick Clifton2000-12-022-2/+5
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* Add MIPS V and MIPS 64 machine numbersNick Clifton2000-12-022-0/+8
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* Add MIPS32 as a seperate MIPS architectureNick Clifton2000-12-012-250/+268
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* Improve MIPS32 supportNick Clifton2000-12-012-20/+35
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* gas/Jakub Jelinek2000-10-202-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/tc-sparc.c (sparc_ip): Fix a bug which caused v9_arg_p instructions to loose any special insn->architecture mask. * config/tc-sparc.c (v9a_asr_table): Add v9b ASRs. (sparc_md_end, sparc_arch_types, sparc_arch, sparc_elf_final_processing): Handle v8plusb and v9b architectures. (sparc_ip): Handle siam mode operands. Support v9b ASRs (and request v9b architecture if they are used). bfd/ * elf32-sparc.c (elf32_sparc_merge_private_bfd_data, elf32_sparc_object_p, elf32_sparc_final_write_processing): Support v8plusb. * elf64-sparc.c (sparc64_elf_merge_private_bfd_data, sparc64_elf_object_p): Support v9b. * archures.c: Declare v8plusb and v9b machines. * bfd-in2.h: Ditto. * cpu-sparc.c: Ditto. include/opcode/ * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. Note that '3' is used for siam operand. opcodes/ * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. (compute_arch_mask): Add v8plusb and v9b machines. (print_insn_sparc): siam mode decoding, accept ASRs up to 25. * opcodes/sparc-opc.c: Support for Cheetah instruction set. (prefetch_table): Add #invalidate.
* Fix ia64 gas testsuite. Update ia64 DV tables. Fix ia64 gas testsuite again.Jim Wilson2000-09-222-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | gas/ChangeLog * config/tc-ia64.c (dv_sem): Add "stop". (specify_resource, case IA64_RS_PR): Only handles regs 1 to 15 now. (specify_resource, case IA64_RS_PRr): New for regs 16 to 62. (specify_resource, case IA64_RS_PR63): Reorder (note == 7) test to match above. (mark_resources): Check IA64_RS_PRr. gas/testsuite/ChangeLog * gas/ia64/dv-raw-err.s: Add new testcases for PR%, 16 - 62. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/dv-imply.d: Regenerate. * gas/ia64/dv-mutex.d, gas/ia64/dv-raw-err.l, gas/ia64/dv-safe.d, gas/ia64/dv-srlz.d, gas/ia64/dv-war-err.l, gas/ia64/dv-waw-err.l, gas/ia64/opc-f.d, gas/ia64/opc-i.d, gas/ia64/opc-m.d: Likewise. include/opcode/ChangeLog * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. opcodes/ChangeLog * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. * ia64-asmtab.c: Regnerate.
* Add support for the MIPS32Nick Clifton2000-09-142-17/+58
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* doco addition.Alan Modra2000-09-052-1/+7
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* Fix 3 DV bugs, and a few minor cleanups.Jim Wilson2000-08-162-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | gas/ * config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle postincrement modified registers. Handle IA64_OPND_R3_2 addl source registers. (note_register_values): Handle IA64_OPND_R3_2 operands. gas/testsuite/ * gas/ia64/dv-raw-err.s: Add new tests for addl and postinc. * gas/ia64/dv-raw-err.l: Likewise. * gas/ia64/dv-waw-err.l: Update sed pattern. * gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment. * gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate. include/opcode/ * ia64.h (IA64_OPCODE_POSTINC): New. opcodes/ * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete break, mov-immediate, nop. * ia64-opc-f.c: Delete fpsub instructions. * ia64-opc-m.c: Add POSTINC to all instructions with postincrement address operand. Rewrite using macros to avoid long lines. * ia64-opc.h (POSTINC): Define. * ia64-asmtab.c: Regenerate.
* 2000-08-15 H.J. Lu <hjl@gnu.org>H.J. Lu2000-08-162-2/+7
| | | | | * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the IgnoreSize change.
* gas:Jason Eckhardt2000-08-091-29/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2000-08-08 Jason Eckhardt <jle@cygnus.com> * config/tc-i860.h: Rework completely for BFD_ASSEMBLER. (i860_fix_info): New enum. (MD_APPLY_FIX3): Define. (WORKING_DOT_WORD): Define. (TC_HANDLES_FX_DONE): Define. (DIFF_EXPR_OK): Define. (LISTING_HEADER): Define. (TARGET_FORMAT): Select target format based on endian flag. (TARGET_BYTES_BIG_ENDIAN): Default to little endian. (target_big_endian): Add external declaration. * config/tc-i860.c: All existing code reworked completely. Other new code shown below. (SYNTAX_SVR4): Define. (target_warn_expand): New variable. (md_shortopts): Declare and define (-Qy, -Qn, and -V options). (md_longopts): Declare and define with new options (-EL, -EB, and -mwarn-expand). (md_show_usage): New function. (md_operand): New function. (obtain_reloc_for_imm16): New function. (md_apply_fix3): New function. (tc_gen_reloc): New function. include: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * opcode/i860.h: Small formatting adjustments. opcode: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * i860-dis.c (print_br_address): Change third argument from int to long. bfd: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * elf32-i860.c (elf32_i860_howto_table): Updated some fields.
* * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros.Denis Chertykov2000-08-062-24/+79
| | | | | Move related opcodes closer to each other. Minor changes in comments, list undefined opcodes.
* 2000-07-22 Jason Eckhardt <jle@cygnus.com>Jason Eckhardt2000-07-281-300/+306
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * include/opcode/i860.h (btne, bte, bla): Changed these opcodes to use sbroff ('r') instead of split16 ('s'). (J, K, L, M): New operand types for 16-bit aligned fields. (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to use I, J, K, L, M instead of just I. (T, U): New operand types for split 16-bit aligned fields. (st.x): Changed these opcodes to use S, T, U instead of just S. (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not exist on the i860. (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. (pfeq.ss, pfeq.dd): New opcodes. (st.s): Fixed incorrect mask bits. (fmlow): Fixed incorrect mask bits. (fzchkl, pfzchkl): Fixed incorrect mask bits. (faddz, pfaddz): Fixed incorrect mask bits. (form, pform): Fixed incorrect mask bits. (pfld.l): Fixed incorrect mask bits. (fst.q): Fixed incorrect mask bits. (all floating point opcodes): Fixed incorrect mask bits for handling of dual bit. * include/elf/i860.h: New file. (elf_i860_reloc_type): Defined ELF32 i860 relocations. * bfd/cpu-i860.c: Added comments. * bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to bfd_elf32_i860_little_vec. (TARGET_LITTLE_NAME): Defined to "elf32-i860-little". (ELF_MAXPAGESIZE): Changed to 4096. * bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of new target. (bfd_target_vector): Added bfd_elf32_i860_little_vec. * bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added config for little endian elf32 i860. (targ_defvec): Define for the new config above as "bfd_elf32_i860_little_vec". (targ_selvecs): Define for the new config above as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec" * bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition of new target vec. * bfd/configure: Regenerated. * opcodes/i860-dis.c: New file. (print_insn_i860): New function. (print_br_address): New function. (sign_extend): New function. (BITWISE_OP): New macro. (I860_REG_PREFIX): New macro. (grnames, frnames, crnames): New structures. * opcodes/disassemble.c (ARCH_i860): Define. (disassembler): Add check for bfd_arch_i860 to set disassemble function to print_insn_i860. * include/dis-asm.h (print_insn_i860): Add prototype. * opcodes/Makefile.in (CFILES): Added i860-dis.c. (ALL_MACHINES): Added i860-dis.lo. (i860-dis.lo): New dependences. * opcodes/configure.in: New bits for bfd_i860_arch. * opcodes/configure: Regenerated.
* 2000-07-26 Dave Brolley <brolley@redhat.com>Dave Brolley2000-07-262-1/+5
| | | | * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned.
* cris.h: New file.Hans-Peter Nilsson2000-07-202-0/+302
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* Applied Marek Michalkiewicz <marekm@linux.org.pl>'s patch to ehance the AVR ↵Nick Clifton2000-06-272-11/+20
| | | | port.
* Applied Stephane Carrez <Stephane.Carrez@worldnet.fr> patches to add supportNick Clifton2000-06-193-1/+423
| | | | for m68hc11 and m68hc12 processors.
* * avr.h: clr,lsl,rol, ... moved after add,adc, ...Denis Chertykov2000-06-092-5/+9
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* * avr.h: New file with AVR opcodes.Denis Chertykov2000-06-072-0/+211
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* Define the ALONE flag bit, for use in the opcode table.Donald Lindsay2000-05-252-0/+5
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* Allow d suffix on iretAlan Modra2000-05-232-2/+7
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* Fix fild.Alan Modra2000-05-172-3/+7
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* * cgen/opcodes fixFrank Ch. Eigler2000-05-162-4/+27
| | | | | | | | | | | | | | | | | | | * approved by nickc [opcodes/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * fr30-desc.h: Partially regenerated to account for changed CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. * m32r-desc.h: Ditto. [include/opcode/ChangeLog] 2000-05-16 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set.
* Fix cpu_flags for sys{enter,exit} fx{save,restore}Alan Modra2000-05-132-5/+9
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* `.arch cpu_type' pseudo for x86.Alan Modra2000-05-132-774/+805
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* Support for tic54x target.Tim Wall2000-05-062-0/+171
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* * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit.J.T. Conklin2000-05-032-0/+13
| | | | (PPC_OPERAND_VR): New operand flag for vector registers.
* * h8300.h (EOP): Add missing initializer.Jeff Law2000-05-012-1/+5
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* * hppa.h (pa_opcodes): New opcodes for PA2.0 wide modeJeff Law2000-04-212-25/+44
| | | | | | | | | forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). New operand types l,y,&,fe,fE,fx added to support above forms. (pa_opcodes): Replaced usage of 'x' as source/target for floating point double-word loads/stores with 'fx'. Fr
* IA-64 ELF support.Jim Wilson2000-04-212-0/+395
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* Fix value of SHORT_A1.Nick Clifton2000-03-272-15/+21
| | | | Move SHORT_AR to end of list of short instructions.
* Mostly cosmetic. Fixes to comments. Don't start as_bad and as_warnAlan Modra2000-03-262-62/+80
| | | | messages with capital. Don't malign Unixware, malign SysV386 instead.
* Apply patch for 100679Nick Clifton2000-03-022-35/+56
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* Extend the i386 gas testsuite to do some tests for intel_syntax. Fix allAlan Modra2000-02-252-2/+7
| | | | | | | the errors exposed by this addition. These were intel mode "fi... word ptr", "fi... dword ptr", "jmp Imm seg, Imm offset", "out dx,al". The failure with intel "out dx,al" was also present in att "out al,dx". Extend testsuite to catch this case too.
* Rename 'flags' to 'signed_overflow_ok_p'Nick Clifton2000-02-242-9/+8
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