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* 2001-10-17 Chris Demetriou <cgd@broadcom.com>Chris Demetriou2001-10-182-1/+6
| | | | | * mips.h: Sort coprocessor instruction argument characters in comment, add a few more words of description for "H".
* [gas/testsuite/ChangeLog]Chris Demetriou2001-10-182-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | 2001-10-17 Chris Demetriou <cgd@broadcom.com> * gas/mips/mips.exp (sb1-ext-ps): New test to test SB-1 core's paired-single extensions to the MIPS64 ISA. * gas/mips/sb1-ext-ps.d: New file. * gas/mips/sb1-ext-ps.s: New file. [include/opcode/ChangeLog] 2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips.h (INSN_SB1): New cpu-specific instruction bit. (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 if cpu is CPU_SB1. [opcodes/ChangeLog] 2001-10-17 Chris Demetriou <cgd@broadcom.com> * mips-dis.c (mips_isa_type): Make the ISA used to disassemble SB-1 binaries include instructions specific to the SB-1. * mips-opc.c (SB1): New definition. (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", "recip.ps", "rsqrt.ps", and "sqrt.ps".
* [gas/ChangeLog]Matthew Green2001-10-172-1/+5
| | | | | | | | | | | | | | | | | | | * config/tc-ppc.c (md_show_usage): Add missing -maltivec, -m7400, -m7410, -m7450 and -m7455 options. [gas/testsuite/ChangeLog] * gas/ppc/altivec.s: New test for AltiVec. * gas/ppc/altivec.d: New file. * gas/ppc/ppc.exp: Test altivec.s [include/opcode/ChangeLog] * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. [opcodes/ChangeLog] * ppc-opc.c (STRM): New AltiVec operand. (XDSS): New AltiVec instruction form. (mtvscr): Correct operand list. (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions.
* oops, fix an error in the previous entry.Matthew Green2001-10-131-2/+3
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* [gas/ChangeLog]Matthew Green2001-10-132-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * config/tc-ppc.c (md_parse_option): New -m7410, -m7450 and -m7455 flags, equivalent to -m7400. New -maltivec to enable AltiVec instructions. New -mbook64 and -mbooke/-mbooke32 flags to enable 64-bit and 32-bit BookE support, respectively. Change -m403 and -m405 to set PPC403 option. (md_show_usage): Adjust for new options. * doc/all.texi: Set PPC. * doc/as.texinfo: Add PPC support and pull in c-ppc.texi. * doc/c-ppc.texi: New file. * doc/Makefile.am (CPU_DOCS): Add c-ppc.texi. * doc/Makefile.in: Regenerate. [gas/testsuite/ChangeLog] * gas/ppc/booke.s: New test for Motorola BookE. * gas/ppc/booke.d: New file. * gas/ppc/ppc.exp: Test booke.s. [include/opcode/ChangeLog] * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_403): New opcode flags for BookE and PowerPC403 instructions. [opcodes/ChangeLog] * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New instruction field instruction/extraction functions for new BookE DE form instructions. (CT): New macro for CT field in an X form instruction. (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form instructions. (PPC64): Don't include PPC_OPCODE_PPC. (403): New opcode macro for PPC403 processors. (BOOKE): New opcode macro for BookE processors. (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look for a disassembler option of `booke', `booke32' or `booke64' to enable BookE support in the disassembler.
* Remove spurious commentNick Clifton2001-09-272-2/+5
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* fix compile time warning messagesNick Clifton2001-09-212-1/+5
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* * alpha.h (struct alpha_operand): Pack elements into bitfields.Richard Henderson2001-09-052-4/+8
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* mips3264 supportEric Christopher2001-08-312-1/+4
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* * ppc.h (PPC_OPERAND_DS): Define.Alan Modra2001-08-272-1/+7
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* For include/opcode:Andreas Jaeger2001-08-264-40/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * d30v.h: Fix declaration of reg_name_cnt. * d10v.h: Fix declaration of d10v_reg_name_cnt. * arc.h: Add prototypes from opcodes/arc-opc.c. For opcodes: * tic54x-dis.c: Add unused attributes where needed. * z8k-dis.c (output_instr): Add unused attribute. * h8300-dis.c: Add missing prototypes. (bfd_h8_disassemble): Make static. * cris-dis.c: Add missing prototype. * h8500-dis.c: Likewise. * m68hc11-dis.c: Likewise. * pj-dis.c: Likewise. * tic54x-dis.c: Likewise. * v850-dis.c: Likewise. * vax-dis.c: Likewise. * w65-dis.c: Likewise. * z8k-dis.c: Likewise. * d10v-dis.c: Add missing prototype. (dis_long): Remove unused variable. (dis_2_short): Likewise. * sh-dis.c: Add missing prototypes. * v850-opc.c: Likewise. Add unused attributes where needed. * ns32k-dis.c: Add missing prototypes. (bit_extract_simple): Remove unused variable.
* Add support for MIPS R1[02]000 performance counter opcodes.Thiemo Seufer2001-08-162-1/+10
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* * opcode/mips.h (INSN_GP32): Remove.Richard Sandiford2001-08-101-11/+5
| | | | | (OPCODE_IS_MEMBER): Remove gp32 parameter. (M_MOVE): New macro identifier.
* Revert 2001-08-08 changes.Alan Modra2001-08-102-1/+4
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* * ppc.h (struct powerpc_operand): New field `reloc'.Alan Modra2001-08-082-0/+6
| | | | | * ppc-opc.c: Include "bfd.h". (powerpc_operands): Add new field for reloc type.
* 2001-08-01 Aldy Hernandez <aldyh@redhat.com>Aldy Hernandez2001-08-011-1/+1
| | | | * include/opcode/mips.h (INSN_ISA_MASK): Nuke bits 12-15.
* 2001-07-12 Jeff Johnston <jjohnstn@redhat.com>Jeff Johnston2001-07-121-0/+10
| | | | | * opcode/cgen.h (CGEN_INSN): Add regex support. (build_insn_regex): Declare.
* * some support for funny-endian 16/32-bit insn setsFrank Ch. Eigler2001-07-122-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | [cgen/ChangeLog] 2001-07-11 Frank Ch. Eigler <fche@redhat.com> * desc-cpu.scm (-gen-mach-table-defns): Emit fourth field: the mach->cpu insn-chunk-bitsize. (-gen-cpu-open): In @arch@_cgen_rebuild_tables, process above new field toward CGEN_CPU_TABLE->insn_chunk_bitsize. * mach.scm (<cpu>): New field insn-chunk-bitsize. (-cpu-parse, -cpu-read): Parse/initialize it. * doc/rtl.texi (define-cpu): Document it. [opcodes/ChangeLog] 2001-07-11 Frank Ch. Eigler <fche@redhat.com> * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of bfd_get_bits. * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect non-zero CGEN_CPU_DESC->insn_chunk_bitsize. [include/opcode/ChangeLog] 2001-07-11 Frank Ch. Eigler <fche@redhat.com> * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. (cgen_cpu_desc): Ditto.
* 2001-07-07 Ben Elliston <bje@redhat.com>Ben Elliston2001-07-062-313/+331
| | | | * m88k.h: Clean up and reformat. Remove unused code.
* Index: opcodes/ChangeLogGeoffrey Keating2001-06-142-0/+9
| | | | | | | | | | | | | | | | | | | | | 2001-06-13 Geoffrey Keating <geoffk@redhat.com> * cgen-asm.c (cgen_parse_keyword): When looking for the boundaries of a keyword, allow any special characters that are actually in one of the allowed keyword. * cgen-opc.c (cgen_keyword_add): Add any special characters to the nonalpha_chars field. Index: cgen/ChangeLog 2001-06-13 Geoffrey Keating <geoffk@redhat.com> * desc.scm (<keyword> 'gen-defn): Add extra zero into CGEN_KEYWORD_ENTRY initializers. Index: include/opcode/ChangeLog 2001-06-13 Geoffrey Keating <geoffk@redhat.com> * cgen.h (cgen_keyword): Add nonalpha_chars field.
* Fix some entries.Alan Modra2001-05-281-1/+1
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* Add MIPS r12k supportNick Clifton2001-05-232-0/+5
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* 2001-05-23 John Healy <jhealy@redhat.com>John Healy2001-05-232-1/+5
| | | | * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48.
* Fix MIPS disassembler so that it produces reassemblable code.Nick Clifton2001-05-152-0/+5
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* Correct cvtps2dq, movdq2q, movq2dq, and movq problems.Alan Modra2001-05-122-3/+9
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* Assorted fixes to pinsrw, pextrw, pmovmskb, movmskp, maskmovq.Alan Modra2001-05-042-4/+9
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* * cris.h (enum cris_insn_version_usage): Correct comment forHans-Peter Nilsson2001-04-052-2/+7
| | | | cris_ver_v3p.
* Small tweaks to sse2 instructions.Alan Modra2001-03-242-2/+8
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* * cris.h (ADD_PC_INCR_OPCODE): New macro.Hans-Peter Nilsson2001-03-222-0/+6
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* 2001-03-21 Kazu Hirata <kazu@hxi.com>Kazu Hirata2001-03-222-7/+7
| | | | * h8300.h: Fix formatting.
* paddq and psubq support.Alan Modra2001-03-222-0/+8
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* Fix register name printed in warning message.Alan Modra2001-03-192-0/+7
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* Fix typos in ChangeLogs; add coff/external.h; fix copyright datesNick Clifton2001-03-1430-51/+135
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* new defines for Coldfire V4.Nick Clifton2001-02-282-2/+9
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* Add PDP-11 supportNick Clifton2001-02-182-4/+86
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* * i386.h (i386_optab): SSE integer converison instructions haveJan Hubicka2001-02-122-6/+11
| | | | | | | 64bit versions on x86-64. * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison instructions. (putop): Handle 'Y'
* Remove extraneous whitespaceNick Clifton2001-02-102-12/+18
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* Add s390 supportNick Clifton2001-02-102-0/+134
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* Binutils portion of fix for syntax array elements when maxPatrick Macdonald2001-02-022-9/+11
| | | | | | | | | | | | | operands is greater than 127. 2001-02-02 Patrick Macdonald <patrickm@redhat.com> * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. * m32r-desc.h: Regenerate.
* Fix swapgs instruction.Alan Modra2001-01-242-3/+7
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* Adds assembly and dis-assembly support for the HPPA wideAlan Modra2001-01-142-21/+35
| | | | mode, 16 bit forms of ldi, ldo, ldw and stw instructions.
* * i386.c (md_assemble): Check cpu_flags even for nullary instructions.Jan Hubicka2001-01-132-3/+9
| | | | | | | * i386.h (i386_optab): Fix pusha and ret templates. * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret templates.
* Updated ARC assembler from arccores.comNick Clifton2001-01-112-106/+155
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* * i386.h (pinsrw): Add.Jan Hubicka2001-01-102-4/+12
| | | | | | | (pshufw): Remove. (cvttpd2dq): Fix operands. (cvttps2dq): Likewise. (movq2q): Rename to movdq2q.
* Fix "movnti"Alan Modra2001-01-102-6/+10
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* 2001-01-09 Jeff Johnston <jjohnstn@redhat.com>Jeff Johnston2001-01-092-3/+15
| | | | | | | * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number of operands (unsigned char or unsigned short). (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char.
* * tc-i386.c (md_assemble): Handle third byte of the opcode as prefix.Jan Hubicka2001-01-052-5/+9
| | | | * i386.h (i386_optab): Make [sml]fence template to use immext field.
* * tc-i386.h (CpuK6, CpuAthlon, CpuSledgehammer, CpuMMX, Cpu3dnow,Jan Hubicka2001-01-032-4/+173
| | | | | | | | | CpuUnknown): Renumber (CpuP4, CpuSSE2): New. (CpuUnknownFlags): Add CpuP4 and CpuSSE2 * i386.h (i386_optab): Fix 64bit pushf template; Add instructions introduced by Pentium4
* * configure.in: Add support for x86_64 and x86_64-*-linux-gnu*Jan Hubicka2000-12-302-272/+452
| | | | | | | | | | | | | * NEWS: Add x86_64. * i386.h (i386_optab): Add "rex*" instructions; add swapgs; disable jmp/call far direct instructions for 64bit mode; add syscall and sysret; disable registers for 0xc6 template. Add 'q' suffixes to extendable instructions, disable obsoletted instructions, add new sign/zero extension ones. (i386_regtab): Add extended registers. (*Suf): Add No_qSuf. (q_Suf, wlq_Suf, bwlq_Suf): New.
* * tc-i386.h (i386_target_format): Define even for ELFs.Jan Hubicka2000-12-202-107/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | (QWORD_MNEM_SUFFIX): New macro. (CpuK6,CpuAthlon,CpuSledgehammer, Cpu64, CpuNo64, CpuUnknownFlags): New macros (CpuMMX,CpuSSE,Cpu3dnow, CpuUnknown): Renumber. (IgnoreSize, DefaultSize, No_?Suf, FWait, IsString, regKludge, IsPrefix, ImmExt): Renumber. (Size64, No_qSuf, NoRex64, Rex64): New macros. (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros. (Imm8, Imm8S, Imm16, Imm32, Imm1, BaseIndex, Disp8, Disp16, Disp32, InOutPortReg,ShiftCount, Control, Debug, Test, FloatReg, FloatAcc, SReg2, SReg3, Acc, JumpAbsolute, RegMMX, RegXMM, EsSeg, InvMem): Renumber. (Reg, WordReg): Add Reg64. (Imm): Add Imm32S and Imm64. (EncImm): New. (Disp): Add Disp64 and Disp32S. (AnyMem): Add Disp32S. (RegRex, RegRex64): New macros. (rex_byte): New type. * tc-i386.c (set_16bit_code_flag): Kill. (fits_in_unsigned_long, fits_in_signed_long): New functions. (reloc): New parameter "signed"; support x86_64. (set_code_flag): New. (DEFAULT_ARCH): New macro; default to "i386". (default_arch): New static variable. (struct _i386_insn): New fields Operand_PCrel; rex. (flag_16bit_code): Kill; All tests replaced to "flag_code == CODE_64BIT"; (flag_code): New enum and static variable. (use_rela_relocations): New static variable. (flag_code_names): New static variable. (cpu_arch_flags): Default to CpuUnknownFlags|CpuNo64. (cpu_arch): Add "sledgehammer"; Add CPUAthlon to Athlon and CpuK6 to K6 and Athlon. (i386_align_code): Return plain "nop" for x86_64. (mode_from_disp_size): Support Disp32S. (smallest_imm_type): Support Imm32S and Imm64. (offset_in_range): Support size of 8. (set_cpu_arch): Do not clobber to Cpu64/CpuNo64. (md_pseudo_table): Add "code64"; use set_code_flat. (md_begin): Emit sane error message on hash failure. (tc_i386_fix_adjustable): Support x86_64 relocations. (md_assemble): Support QWORD_MNEM_SUFFIX, REX registers, instructions supported on particular arch just partially, output of 64bit immediates, handling of Imm32S and Disp32S type. (i386_immedaite): Support x86_64 relocations; support 64bit constants. (i386_displacement): Likewise. (i386_index_check): Cleanup; support 64bit addresses. (md_apply_fix3): Support x86_64 relocation and rela. (md_longopts): Add "32" and "64". (md_parse_option): Add OPTION_32 and OPTION_64. (i386_target_format): Call even for ELFs; choose between elf64-x86-64 and elf32-i386. (i386_validate_fix): Refuse GOTOFF in 64bit mode. (tc_gen_reloc): Support rela relocations and x86_64. (intel_e09_1): Support QWORD. * i386.h (i386_optab): Replace "Imm" with "EncImm". (i386_regtab): Add flags field.
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