From f1aeb3c82ab5e041d31034146c5d070f98316c20 Mon Sep 17 00:00:00 2001 From: Chris Demetriou Date: Tue, 30 Sep 2003 16:17:14 +0000 Subject: [ bfd/ChangeLog ] 2003-09-30 Chris Demetriou * archures.c (bfd_mach_mipsisa64r2): New define. * bfd-in2.h: Regenerate. * aoutx.h (NAME(aout,machine_type)): Handle bfd_mach_mipsisa64r2. * cpu-mips.c (I_mipsisa64r2): New enum value. (arch_info_struct): Add entry for I_mipsisa64r2. * elfxx-mips.c (_bfd_elf_mips_mach) (_bfd_mips_elf_print_private_bfd_data): Handle E_MIPS_ARCH_64R2. (mips_set_isa_flags): Add bfd_mach_mipsisa64r2 case. (mips_mach_extensions): Add entry for bfd_mach_mipsisa64r2. [ binutils/ChangeLog ] 2003-09-30 Chris Demetriou * readelf.c (get_machine_flags): Handle E_MIPS_ARCH_64R2. [ gas/Changelog ] 2003-09-30 Chris Demetriou * configure.in (mipsisa64r2, mipsisa64r2el, mipsisa64r2*): New CPUs. * configure: Regenerate. * config/tc-mips.c (imm2_expr): New variable. (md_assemble, mips16_ip): Initialize imm2_expr. (ISA_HAS_64BIT_REGS, ISA_HAS_DROR, ISA_HAS_ROR): Add ISA_MIPS64R2. (macro_build): Handle +A, +B, +C, +E, +F, +G, and +H format operands. (macro): Handle M_DEXT and M_DINS. (validate_mips_insn): Handle +E, +F, +G, +H, and +I format operands. (mips_ip): Likewise. (OPTION_MIPS64R2): New define. (md_longopts): New entry for -mips64r2 (OPTION_MIPS64R2). OPTION_ASE_BASE): Increase to compensate for OPTION_MIPS64R2. (md_parse_option): Handle OPTION_MIPS64R2. (s_mipsset): Handle setting "mips64r2" ISA. (mips_cpu_info_table): Add mips64r2. (md_show_usage): Document -mips64r2 option. * doc/as.texinfo: Docuemnt -mips64r2 option. * doc/c-mips.texi: Likewise. [ gas/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou * gas/mips/cp0-names-mips64r2.d: New file. * gas/mips/cp0sel-names-mips64r2.d: New file. * gas/mips/elf_arch_mips64r2.d: New file. * gas/mips/hwr-names-mips64r2.d: New file. * gas/mips/mips32r2-ill-fp64.l: New file. * gas/mips/mips32r2-ill-fp64.s: New file. * gas/mips/mips64r2-ill.l: New file. * gas/mips/mips64r2-ill.s: New file. * gas/mips/mips64r2.d: New file. * gas/mips/mips64r2.s: New file. * gas/mips/mips.exp: Define "mips64r2" arch, and run new tests. [ include/elf/ChangeLog ] 2003-09-30 Chris Demetriou * mips.h (E_MIPS_ARCH_64R2): New define. [ include/opcode/ChangeLog ] 2003-09-30 Chris Demetriou * mips.h: Document +E, +F, +G, +H, and +I operand types. Update documentation of I, +B and +C operand types. (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. (M_DEXT, M_DINS): New enum values. [ ld/ChangeLog ] 2003-09-30 Chris Demetriou * ldmain.c (get_emulation): Ignore "-mips64r2". [ ld/testsuite/ChangeLog ] 2003-09-30 Chris Demetriou * ld-mips-elf/mips-elf-flags.exp: Add tests for combinations with MIPS64r2. [ opcodes/ChangeLog ] 2003-09-30 Chris Demetriou * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" (print_insn_args): Add handing for +E, +F, +G, and +H. * mips-opc.c (I65): New define for MIPS64r2. (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to be supported on MIPS64r2. --- include/opcode/mips.h | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) (limited to 'include/opcode/mips.h') diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 65434a778..9dab62060 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -236,11 +236,24 @@ struct mips_opcode "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" occur first to set position. + Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. + (Also used by "dext" w/ different limits, but limits for + that are checked by the M_DEXT macro.) + "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + Enforces: 32 <= pos < 64. + "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. + "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). + Requires that "+A" or "+E" occur first to set position. + Enforces: 32 < (pos+size) <= 64. Floating point instructions: "D" 5 bit destination register (OP_*_FD) @@ -265,7 +278,8 @@ struct mips_opcode Macro instructions: "A" General 32 bit expression - "I" 32 bit immediate + "I" 32 bit immediate (value placed in imm_expr). + "+I" 32 bit immediate (value placed in imm2_expr). "F" 64 bit floating point constant in .rdata "L" 64 bit floating point constant in .lit8 "f" 32 bit floating point constant @@ -292,7 +306,7 @@ struct mips_opcode Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: - "ABCD" + "ABCDEFGHI" */ /* These are the bits which may be set in the pinfo field of an @@ -385,6 +399,7 @@ struct mips_opcode #define INSN_ISA32 0x00000020 #define INSN_ISA64 0x00000040 #define INSN_ISA32R2 0x00000080 +#define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ #define INSN_ASE_MASK 0x0000f000 @@ -432,6 +447,8 @@ struct mips_opcode #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) +#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) + /* CPU defines, use instead of hardcoding processor number. Keep this in sync with bfd/archures.c in order for machine selection to work. */ @@ -460,6 +477,7 @@ struct mips_opcode #define CPU_MIPS32R2 33 #define CPU_MIPS5 5 #define CPU_MIPS64 64 +#define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ /* Test for membership in an ISA including chip specific ISAs. INSN @@ -542,6 +560,8 @@ enum M_DDIV_3I, M_DDIVU_3, M_DDIVU_3I, + M_DEXT, + M_DINS, M_DIV_3, M_DIV_3I, M_DIVU_3, -- cgit v1.2.3